Hynix HMP125U6EFR8C-S6 Manuale Utente
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DDR2 Device Operations & Timing Diagram
1.2 Basic Function & Operation of DDR2 SDRAM
Read and write accesses to the DDR2 SDRAM are burst oriented; accesses start at a selected location and
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of
an Active command, which is then followed by a Read or Write command. The address bits registered coinci-
dent with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank;
A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to
select the starting column location for the burst access and to determine if the auto precharge command is to
be issued.
continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of
an Active command, which is then followed by a Read or Write command. The address bits registered coinci-
dent with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank;
A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to
select the starting column location for the burst access and to determine if the auto precharge command is to
be issued.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed infor-
mation covering device initialization, register definition, command descriptions and device operation.
mation covering device initialization, register definition, command descriptions and device operation.
1.2.1 Power up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
than those specified may result in undefined operation.
Power-up and Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power and attempt to maintain CKE below 0.2*VDDQ and ODT
*1
at a LOW state (all other inputs
may be undefined.)
- VDD, VDDL and VDDQ are driven from a single power converter output, AND
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
- VTT is limited to 0.95 V max, AND
- Vref tracks VDDQ/2.
or
- Apply VDD before or at the same time as VDDL.
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
- Apply VDDL before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.
at least one of these two sets of conditions must be met.
2. Start clock and maintain stable condition.
3. For the minimum of 200
3. For the minimum of 200
us after stable power and clock(CK, CK), then apply NOP or deselect & take
CKE HIGH.
4. Wait minimum of 400ns then issue precharge all command. NOP or deselect applied during 400ns
period.
5. Issue EMRS command to EMR(2). (To issue EMRS command to EMR(2), provide “LOW” to BA0 and
BA2, “HIGH” to BA1.)
*2
6. Issue EMRS command to EMR(3). (To issueEMRS command to EMR(3), provide “LOW” to BA2, “HIGH”
to BA0 and BA1.)
*2
7. Issue EMR to enable DLL. (To issue "DLL Enable" command, provide "LOW" to A0, "HIGH" to BA0 and
"LOW" to BA1-2 and A13~A15. And A9=A8=A7=LOW must be sued when issuing this command)
8. Issue a Mode Register set command for “DLL reset”.
(To issue DLL reset command, provide "HIGH" to A8 and "LOW" to BA0-2, and A13~15.)
9. Issue precharge all command.
10. Issue 2 or more auto-refresh commands.
11. Issue a mode register command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration ( Off Chip Driver impedance adjustment ).