Intel Pentium 4 M RH80532GC041512 Manuale Utente
Codici prodotto
RH80532GC041512
Mobile Intel
Pentium
4 Processor-M Datasheet
5
Figures
Illustration of Deep Sleep VCC Static and Transient Tolerances (VID
Setting = 1.30 V) ................................................................................................. 29
Setting = 1.30 V) ................................................................................................. 29
ITPCLKOUT[1:0] Output Buffer Diagram ............................................................ 34
TCK Clock Waveform.......................................................................................... 41
System Bus Common Clock Valid Delay Timings............................................... 43
System Bus Reset and Configuration Timings.................................................... 44
Source Synchronous 2X (Address) Timings ....................................................... 44
Source Synchronous 4X Timings ........................................................................ 45
Power Up Sequence ........................................................................................... 46
Power Down Sequence....................................................................................... 46
BCLK Signal Integrity Waveform......................................................................... 52
Low-to-High System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers ................................................................................................................. 54
Buffers ................................................................................................................. 54
High-to-Low System Bus Receiver Ringback Tolerance for PWRGOOD and TAP
Buffers ................................................................................................................. 54
Buffers ................................................................................................................. 54
Micro-FCPGA Package - Bottom View................................................................ 64
The Coordinates of the Processor Pins as Viewed From the Top of the
Package. ............................................................................................................. 65
Package. ............................................................................................................. 65
Clock Control States............................................................................................ 94