Philips S1D13505 Manuale Utente

Page 12

Vancouver Design Center

S1D13505

Hardware Functional Specification

X23A-A-001-14

Issue Date: 01/02/02

• 16-bit DRAM interface:

• EDO-DRAM up to 40MHz data rate (80M bytes/sec.).

• FPM-DRAM up to 25MHz data rate (50M bytes/sec.).

• Memory size options:

• 512K bytes using one 256K

×

16 device.

• 2M bytes using one 1M

×

16 device.

• Performance Enhancement Register to tailor the memory control output timing for the DRAM 

device.

• Supports the following interfaces:

• 8/16-bit SH-4 bus interface.

• 8/16-bit SH-3 bus interface.

• 8/16-bit interface to 8/16/32-bit MC68000 microprocessors/microcontrollers.

• 8/16-bit interface to 8/16/32-bit MC68030 microprocessors/microcontrollers.

• Philips PR31500/PR31700 (MIPS).

• Toshiba TX3912 (MIPS)

• 16-bit Power PC (MPC821) microprocessor.

• 16-bit Epson E0C33 microprocessor.

• PC Card (PCMCIA).

• StrongARM (PC Card).

• NEC VR41xx (MIPS).

• ISA bus.

• Supports the following interface with external logic:

• GX486 microprocessor.

• One-stage write buffer for minimum wait-state CPU writes.

• Registers are memory-mapped – the M/R# pin selects between the display buffer and register 

address space.

• The complete 2M byte display buffer address space is addressable as a single linear address 

space through the 21-bit address bus.