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Emerson PMPPC7448 Manuale Utente

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CPLD:
 Interrupt Registers
7-4
Interrupt Enable Register (IER)
Register 7-4:
PmPPC7448 Interrupt Enable Register (IER) at 0xf820,2000
R:
Reserved (default is 000)
SR0EN:
PCI0 SERR Enable interrupt routed from PCI0 SERR to MV64460
1 Enabled to generate an interrupt
0 Disabled (default)
PR0EN:
PCI0 PERR Enable interrupt routed from PCI0 PERR to MV64460
1 Enabled to generate an interrupt
0 Disabled (default)
Interrupt Pending Register (IPR)
This register allows software to determine which source has caused an interrupt.
Register 7-5:
PmPPC7448 Interrupt Pending Register (IPR) at 0xf820,3000
R:
Reserved (default is 000)
SERR0:
PCI0 SERR Enable
1 SERR has occurred and is enabled (IER SR1EN=1)
0 No SERR (default)
PERR0:
PCI0 PERR Enable
1 PERR has occurred and is enabled (IER PR1EN=1)
0 No  PERR  (default)
7
6
5
4
3
2
1
0
Reserved
SR0EN
PR0EN
7
6
5
4
3
2
1
0
Reserved
SERR0
PERR0