NEC PD75P402 Manuale Utente

The STOP mode is reset only by RESET input. The HALT mode is reset by standby release signal by setting of

an interrupt request flag enabled by the interrupt enable flag and by RESET input.

The standby mode reset operation is shown in Fig. 7-1.

µ

When the RESET input drops from high to low, the oscillator begins to oscillate simultaneously with entry into

the reset state.

When the RESET input level returns from low to high, instruction execution begins even if oscillation is unstable.

Therefore, provide an oscillation stabilization time by making the RESET input low level sufficiently wide.

When the reset state is released, the program branches to the reset start address.

This is different from normal reset operation because the contents of data memory before STOP mode setting

are retained.

When the RESET input drops from high to low, the HALT mode is reset and the 

µ

PD75402A enters the reset state.

When the RESET input level returns from low to high, the program branches to the reset start address and

instruction execution begins.

This is different from the normal reset operation because the contents of data memory before HALT mode setting

are retained.

When an interrupt request flag enabled by interrupt enable flag is set (1), a standby release signal is generated

and the HALT mode is reset. However, the INT0 interrupt request does not generate the standby release signal.