NEC PD75P402 Manuale Utente

The clock generation circuit generates the CPU clock ( 

Φ 

) and various clocks for supply to peripheral hardware,

and controls the CPU operating mode, such as standby mode etc.

Clock generation circuit operation is determined by the processor clock control register (PCC).

Upon RESET input, the PCC is cleared to 0000 and the 

µ

PD75402A operates in low-speed mode (15.3 

µ

s: when

operating at 4.19 MHz).

Peripheral hardware is supplied with various clocks scaled from the system clock generation circuit output (f

XX

in the case of crystal/ceramic oscillation, and f

X

 when an external clock is used) by the frequency divider.

From this section on, only f

XX 

 is used when expressing the speed of the various clocks; for an external clock, this

should be replaced by f

X

.

The operation of each block is described below.

The PCC is a 4-bit register which performs selection of the CPU clock 

Φ

 and control of the CPU operating mode.

The format of the PCC is shown in Fig. 5-11.

When bit 3 or bit 2 is set (1), standby mode is selected. When standby mode is released by the Standby Release

signal, both bits are automatically cleared and the normal operating mode is reestablished (see CHAPTER 7

“STANDBY FUNCTION” for details).Setting of the low-order 2 bits of the PCC is performed by a 4-bit memory

handling instruction. At this time, ensure that bits 3 and 2 are reset to “0” so that the pattern “00

××

” is written.

Bits 3 and 2 are set (1) by the STOP instruction and the HALT instruction respectively.

RESET input clears the PCC to 0000.

To set the machine cycle to 0.95 

µ

s (f

XX

 = 4.19 MHz).

SEL

MB15

MOV

 A, #0011B

MOV

PCC, A

To set the machine cycle to 1.63 

µ

s (f

XX

 = 4.91 MHz).

SEL

MB15

MOV

A. # 0010B

MOV

PCC, A

To select the STOP mode. (Be sure to include an NOP instruction after a STOP or HALT instruction.)

STOP

NOP