NEC PD750008 Manuale Utente
84
µPD750008 USER'S MANUAL
5.2 CLOCK GENERATOR
The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU
operation mode.
5.2.1 Clock Generator Configuration
Figure 5-11 shows the configuration of the clock generator.
Figure 5-11. Block Diagram of the Clock Generator
Note Instruction execution
Remarks 1. f
X
: Main system clock frequency
2. f
XT
: Subsystem clock frequency
3.
F
= CPU clock
4. PCC: Processor clock control register
5. SCC: System clock control register
6. One clock cycle (t
CY
) of the CPU clock (
F
) is equal to one machine cycle of an instruction.
Subsystem
clock generator
clock generator
Main system
clock generator
clock generator
Clock timer
• Basic interval timer (BT)
• Timer/event counter
• Timer counter
• Serial interface
• Clock timer
• INT0 noise eliminator
• Clock output circuit
• Timer/event counter
• Timer counter
• Serial interface
• Clock timer
• INT0 noise eliminator
• Clock output circuit
1/1 to 1/4096
Frequency divider
Selec-
tor
tor
Selec-
tor
tor
Frequency
divider
divider
Φ
Oscillator
disable
signal
disable
signal
Internal bus
HALT
Note
STOP
Note
PCC2, PCC3
clear signal
clear signal
Wait release signal from BT
Standby release signal from
interrupt control circuit
interrupt control circuit
RESET signal
XT1
XT2
X1
X2
4
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
STOP flip-flop
Q
S
R
HALT flip-flop
S
Q
R
f
XT
f
X
1/2
1/16
1/4
1/4
•
CPU
•
INT0 noise eliminator
•
Clock output circuit
WM.3