NEC PD17062 Manuale Utente

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An interrupt temporarily stops the program being executed in response to a request from the peripheral

hardware (INT

NC

 pin,  timer, V

SYNC

 pin or serial interface).  The interrupt then branches the program flow to

a predetermined address (vector address).

Fig. 11-1 shows the interrupt block configuration.

The interrupt block consists of the interrupt request control blocks, interrupt enable flip-flop (INTE), stack

pointer, address stack register, program counter, and interrupt stack.  The interrupt request control blocks

control interrupt requests from the INT

NC

 pin, timer, V

SYNC

 pin, and serial interface.  The interrupt enable flip-

flop (INTE) sets all interrupt permissions.  The stack pointer, address stack register, program counter, and

interrupt stack are controlled when an interrupt is accepted.

The interrupt request processing block in the peripheral hardware consists of the IRQ

×××

 flip-flop, IP

×××

flip-flop, and vector address generator (VAG).  The IRQ

×××

 flip-flop detects an interrupt request, the IP

×××

 flip-

flop sets an interrupt permission, and the vector address generator (VAG) specifies a vector address at

interrupt acceptance.

The IRQ

×××

 flip-flop and IP

×××

 flip-flop correspond to the interrupt request flag and interrupt permission

flag, respectively, in the control register in one-to-one ratio.