NEC PD17062 Manuale Utente

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In a program using a timer that operates at constant intervals once a power-on reset occurs, it is necessary

to have the timer interrupt handling routine finish within that constant interval.

This is explained using an example.

BR

AAA

; Branches to AAA after reset.

TIMER:

; Program address 0003H

ADD

M1, #0100B ; Adds 0100B to the content of M1.

SKT1

CY

; Performs clock processing if a carry occurs.

BR

AAA

; 

#

Clock process

EI

RETI

AAA:

INITFLG   NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies the timer interrupt time and timer carry FF setting time interval as 250

and 100 ms, respectively.

SET1

IPBTM0

; Built-in macro

EI

; Enables the timer interrupt.

Process A

BR

AAA

The program in this example performs the clock process 

# at every one second while performing process

A.

If the CE pin goes from a low to a high as shown in Fig. 12-10 (a), a CE reset occurs in synchronization with

the positive-going edge of the timer carry FF set pulse.  If the timer interrupt request happens to be issued

simultaneously when the timer carry FF is set, a CE reset takes precedence.  When the CE reset occurs, it resets

the timer interrupt request (IRQBTM0 flag), thus skipping the timer process once.