NEC PD17062 Manuale Utente

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The CE pin controls the following items according to the level and positive-going edge of its input signal.

(1) Whether to enable or disable the clock stop instruction

(2) Whether to reset the device

Sections 13.3.1 and 13.3.2 explain the above items, respectively.

The clock stop instruction, STOP s, is effective only when the CE pin is at a low level.

If the STOP s instruction is executed when the CE pin is at a high level, it is treated as a no-operation (NOP)

instruction.

Driving the CE pin from a low to a high can reset the device (CE reset).

There is another type of reset, which is a power-on reset.  It occurs when supply voltage V

DD

 is turned on.

See Chapter 14 for details.

The CE pin does not accept a high or low level with a duration of less than 187.5 

µ

s to prevent malfunction

due to noise.

The input level of a signal supplied to the CE pin is checked using the CE flag in the control register (bit

b

0

 at address 07H).

Fig. 13-2 shows the relationship between the input signal and CE flag.

CE pin

CE flag

Less than 187.5 

  

s

Less than 187.5 

  

s

CE reset

STOP instruction disabled (NOP)

STOP instruction enabled

STOP instruction disabled (NOP); 
a CE reset occurs next time 
the timer carry FF is set.

187.5 

  

s

187.5 

  

s

µ

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