NEC PD17062 Manuale Utente

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Table 13-1 summarizes how the CPU and peripheral hardware behave during the halt or clock stop state.

During the halt state, execution of the CPU instructions is suspended, but the peripheral hardware operates

normally, as described in Table 13-1.

During the clock stop state, on the other hand, all peripheral hardware is at a stop.

During the halt state, the control register that controls the operating state of the peripheral hardware works

as usual (not initialized).  During the clock stop state (when the STOP s instruction is executed), on the other

hand, the control register is initialized to a specified value.

To put in another way, the peripheral hardware keeps operating as specified in the control register during

the halt state.  During the clock stop state, however, the peripheral hardware operates according to the initial

value set in the control register.

See Chapter 9 for the initial value for the control register.

Let’s study the following example.

HLTINT

DAT 1000B

; Defines a symbol.

XTAL

DAT 0000B

;

INITFLG

P0ABIO3, P0ABIO2, P0ABIO1, P0ABIO0

; Built-in macro

;  

#

SET2

P0A0, P0A1

;

INITFLG

SIO0CH, NOT SB, SIO0MS, SIO0TX

;

SET2

SIO0CK1, SIO0CK0

;  

$

SET2

SIO0IMD1, SIO0IMD0

CLR1

IRQSIO0

SET1

IPSIO0

EI

;  

%

SET1

SIO0NWT

;  

&

HALT

HLTINT

;  

(

STOP

XTAL

The above program outputs a high level from the P0A

0

 and P0A

1

 pins at 

#, specifies a serial interface

condition at 

$, and starts serial communication at %.

When the HALT instruction is executed at 

&, the serial communication continues, and the halt state is

released after a serial interface interrupt request is accepted.