NEC PD17062 Manuale Utente

µ

Bit position

b

3

b

2

b

1

b

0

Flag name

SIO0CK3

SIO0CK2

SIO0CK1

SIO0CK0

(0)

(0)

SIO0CK1

SIO0CK0   Internal clock frequency

0

0

100 kHz

0

1

200 kHz

1

0

500 kHz

1

1

1 MHz

The shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the

serial interface.

The shift clock frequency register is mapped to address 39H of the register file.

Fig. 16-7 shows the configuration of the shift clock frequency register.  The register is not mapped to the

two high-order bits of the shift clock frequency register.  If the two high-order bits of the shift clock frequency

register are read, 0 is read from each bit.