NEC PD17062 Manuale Utente

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The PLL frequency synthesizer receives an input signal at the VCO pin, divides its frequency in the

programmable divider, and outputs the difference in phase between the divider output and the reference

frequency from the EO pin.

The PLL frequency synthesizer works only when the CE pin is at a high level.  It is disabled when the CE

pin is at a low level.  See Section 18.6 for the disable mode of the PLL frequency synthesizer.

Items (1) to (4) briefly describe each block of the synthesizer.

The programmable divider divides the frequency of a signal input from the VCO pin.  It uses NEC’s

proprietary pulse swallow method to divide a frequency.  A division value is given through the data buffer

(DBF).

See  Section 18.3.

The reference frequency generator generates a reference frequency that the phase comparator (

φ

-DET)

uses for reference purposes.

A reference frequency can be selected using the PLL reference mode select register (at address 13H).

See Section 18.4.

φ

The phase comparator compares the output signal of the programmable divider (PD) with a signal from

the reference frequency generator (RFG) and outputs the phase difference between the signals.  The phase

comparator can also detect the PLL unlock state.

Detection of the PLL unlock state is controlled with the PLL unlock FF delay control register (at address

32H) and the PLL unlock FF judge register (at address 22H).

See Section 18.5.

The charge pump directs the output signal of the phase comparator (

φ

-DET) to the EO pin as a high, low

level, or floating output.

See Section 18.5.