Omega OMB-DAQBOARD-3000 Manuale Utente

 

1-12    Daq Systems and Device Overviews 

988093

 

DaqBoard/3000 Series User’s Manual 

 

This example has all 4 DACs being updated and the 16-bits of digital IO.  These updates are performed at 
the same time as the acquisition pacer clock (also called the scan clock.)  All 4 DACs and the 16-bits of 
pattern digital output are updated at the beginning of each scan.  Note that the DACs will actually take up 
to 4 us after the start of scan to settle on the updated value.  This is due to the amount of time to shift the 
digital data out to the DACs plus the actual settling time of the digital to analog conversion. 
 
The data for the DACs and pattern digital output comes from a PC-based buffer.  The data is streamed 
across the PCI bus to the Daqboard/3000 via DMA. 
 
It is possible to update the DACs and pattern digital output with the DAC pacer clock (either internally 
generated or externally applied.)  In this case, the acquisition input scans are not synchronized to the 
analog outputs or pattern digital outputs.  It is possible to synchronize everything (input scans, DACs, 
pattern digital outputs) to one clock.  That clock can be either internally generated or externally applied. 

Four 32-bit counters are built into the DaqBoard/3000 Series boards. Each of the four counters accepts 
frequency inputs up to 20 MHz.  The high-speed counter channels can be configured on a per-channel 
basis.  Possible configurations include the following modes: 
 

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Reference Note: 

For detailed information regarding the various counter modes refer to Chapter 5,  
Counter Input Configuration Modes. 

 
 
The counters can concurrently monitor time periods, frequencies, pulses, and other event driven 
incremental occurrences directly from encoders, pulse-generators, limit switches, proximity switches, and 
magnetic pick-ups. 

As with all other inputs to the boards, the counter inputs can be read asynchronously under program 
control, or synchronously as part of an analog and digital scan group based on a programmable internal 
timer or an external clock source.  

The boards support quadrature encoders with up to 2 billion pulses per revolution, 20 MHz input 
frequencies, and x1, x2, x4 count modes. With only A-phase and B-phase signals, 2 channels are 
supported. With A-phase, B-phase, and Z-index signals, 1 channel is supported. 

Each input can be debounced from 500 ns to 25.5 ms (total of 16 selections) to eliminate extraneous noise 
or switch induced transients.  Encoder input signals must be within -15V to +15V and the switching 
threshold is TTL (1.3V). Power is available for encoders, +5V at up to 500 mA.