Motorola PRPMC800A/IH5 Manuale Utente
PrPMC800/800ET Processor PMC Module Installation and Use (PrPMC800A/IH5)
3 Functional Description
20
Onboard Bank A Flash
The PrPMC800/800ET contains one bank of 32MB of flash memory on Xport 0 configured for
16-bit mode. Bank A consists of two Intel StrataFlash (28F128J3A) +3.3 volt devices configured
to operate in 8-bit mode. These Intel StrataFlash devices support page read mode operations
with an 8-byte page size per device.
16-bit mode. Bank A consists of two Intel StrataFlash (28F128J3A) +3.3 volt devices configured
to operate in 8-bit mode. These Intel StrataFlash devices support page read mode operations
with an 8-byte page size per device.
Optional Bank B Flash
The signal interface for the Harrier Xport 1, configured to operate in Hawk 16-bit address/data
mode, is routed to the PMC P14 connector to support an optional 16-bit flash bank B on the
baseboard. The address multiplexing of the Hawk mode can address up to 512MB, but device
loading may restrict this size to less than that. The reset vector may be sourced by either bank
A or bank B depending on the state of the Harrier Xport reset vector control bits
(RVEN0/RVEN1). When the RVEN0 bit is set, address range $FFF00000-$FFFFFFFF maps to
bank A. When RVEN0 bit is cleared and the RVEN1 bit is set, the address range $FFF00000-
$FFFFFFFF maps to bank B. The default state uses bank A for the reset vector. Bank B may
be selected by connecting the BANKB_SEL pin on P14 to +3.3V.
mode, is routed to the PMC P14 connector to support an optional 16-bit flash bank B on the
baseboard. The address multiplexing of the Hawk mode can address up to 512MB, but device
loading may restrict this size to less than that. The reset vector may be sourced by either bank
A or bank B depending on the state of the Harrier Xport reset vector control bits
(RVEN0/RVEN1). When the RVEN0 bit is set, address range $FFF00000-$FFFFFFFF maps to
bank A. When RVEN0 bit is cleared and the RVEN1 bit is set, the address range $FFF00000-
$FFFFFFFF maps to bank B. The default state uses bank A for the reset vector. Bank B may
be selected by connecting the BANKB_SEL pin on P14 to +3.3V.
Xport 1 may be configured to operate in the normal data byte ordering mode where the data
alternates every byte instead of every forth byte (Hawk data mode). The data ordering mode is
controlled by one of the onboard jumpers.
alternates every byte instead of every forth byte (Hawk data mode). The data ordering mode is
controlled by one of the onboard jumpers.
ECC Memory
The PrPMC800/800ET supports onboard ECC SDRAM configured as explained below.
Onboard SDRAM
The PrPMC800/800ET onboard ECC SDRAM memory, bank A, is configured as one bank of
nine 8-bit wide, +3.3V SDRAM devices in 54-pin TSOPII packages. The total onboard memory
size can be 64MB, 128MB, 256MB, or 512MB depending on the memory type used. The
SDRAM memory is controlled by the Harrier ASIC which provides single-bit error correction and
double-bit error detection. ECC is calculated over 72-bits. Refer to the Harrier ASIC
Programmer’s Reference Guide for additional information and programming details. The
SDRAM memory bus operates at the same speed as the processor bus.
nine 8-bit wide, +3.3V SDRAM devices in 54-pin TSOPII packages. The total onboard memory
size can be 64MB, 128MB, 256MB, or 512MB depending on the memory type used. The
SDRAM memory is controlled by the Harrier ASIC which provides single-bit error correction and
double-bit error detection. ECC is calculated over 72-bits. Refer to the Harrier ASIC
Programmer’s Reference Guide for additional information and programming details. The
SDRAM memory bus operates at the same speed as the processor bus.
SROM
The PrPMC800/800ET
module contains two 8Kb serial EEPROM devices (AT24C64) and one
256 byte serial EEPROM device (AT24C02) onboard. One 8Kb serial EEPROM provides for
Vital Product Data (VPD) storage of the module hardware configuration, and the other 8Kb
device provides storage for user configuration data. The contents of the devices are accessed
by providing a two-byte address with the same device ID, instead of the standard one-byte
address as used in the 256 byte devices. The 256 byte device provides for Serial Presence
Detect (SPD) memory configuration information. The Serial EEPROM’s are accessed through
I
Vital Product Data (VPD) storage of the module hardware configuration, and the other 8Kb
device provides storage for user configuration data. The contents of the devices are accessed
by providing a two-byte address with the same device ID, instead of the standard one-byte
address as used in the 256 byte devices. The 256 byte device provides for Serial Presence
Detect (SPD) memory configuration information. The Serial EEPROM’s are accessed through
I
2
C port 0 in the Harrier ASIC. Refer to Appendix B of the PrPMC800/800ET Processor PMC
Module Programmer’s Reference Guide for information on the contents of the VPD and SPD.