NEC PD78P214 Manuale Utente
311
Chapter 12 Interrupt Functions
12
3. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling program (except
when multiple-interrupt handling for nonmaskable interrupts have been enabled by resetting the NMIS bit of the IST register
to 0 during execution of the nonmaskable interrupt handling program) and except a period between a special instruction
described in Section 12.3.5 and an instruction that follows that special instruction. Therefore, nonmaskable interrupts are
accepted, even if the contents of the stack pointer are undefined, for example, right after a reset occurs. At this point, the
contents of the PC and PSW may be transferred to addresses (see Table 3-4 in Section 3.2.5) where writing to any special-
function register is inhibited, depending on the value in the stack pointer. If this occurs, the CPU may hang, unexpected signals
may be output from pins, or an attempt may be made to transfer the contents of the PC or PSW to a location where no RAM
has been installed, thereby making it impossible to return from the nonmaskable interrupt handling program to the main
routine, hence a program crash.
to 0 during execution of the nonmaskable interrupt handling program) and except a period between a special instruction
described in Section 12.3.5 and an instruction that follows that special instruction. Therefore, nonmaskable interrupts are
accepted, even if the contents of the stack pointer are undefined, for example, right after a reset occurs. At this point, the
contents of the PC and PSW may be transferred to addresses (see Table 3-4 in Section 3.2.5) where writing to any special-
function register is inhibited, depending on the value in the stack pointer. If this occurs, the CPU may hang, unexpected signals
may be output from pins, or an attempt may be made to transfer the contents of the PC or PSW to a location where no RAM
has been installed, thereby making it impossible to return from the nonmaskable interrupt handling program to the main
routine, hence a program crash.
If a falling edge (valid edge of the NMI input after a reset) arrives at the NMI pin at much the same time when a rising edge is
supplied to the RESET pin, a branch occurs to the nonmaskable interrupt handling program without executing a single
instruction after a reset, resulting in a program crash almost with no exception. To avoid these problems, initialize the stack
pointer after a reset, and design the hardware so that the NMI signal does not drop within 10
supplied to the RESET pin, a branch occurs to the nonmaskable interrupt handling program without executing a single
instruction after a reset, resulting in a program crash almost with no exception. To avoid these problems, initialize the stack
pointer after a reset, and design the hardware so that the NMI signal does not drop within 10
µ
s + 20/f
CLK
after the RESET signal
rises.
12.3.3 Accepting Maskable Interrupts
A maskable interrupt is accepted when the corresponding interrupt request flag is set to 1, if the corresponding
interrupt mask flag is 0. When a macro service is used, the interrupt is accepted immediately when the interrupt
flag is set to 1. If it is a vectored interrupt, it is accepted when interrupts are enabled (when the IE flag is 1). However,
low-priority interrupts are not accepted if a high-priority interrupt is already being serviced (when the ISP flag is
0).
interrupt mask flag is 0. When a macro service is used, the interrupt is accepted immediately when the interrupt
flag is set to 1. If it is a vectored interrupt, it is accepted when interrupts are enabled (when the IE flag is 1). However,
low-priority interrupts are not accepted if a high-priority interrupt is already being serviced (when the ISP flag is
0).
If two or more maskable interrupt requests occur simultaneously, they are accepted according to their priority (as
specified in the priority specification flag). If interrupt requests have the same priority, an interrupt request with
the highest default priority is accepted first.
specified in the priority specification flag). If interrupt requests have the same priority, an interrupt request with
the highest default priority is accepted first.
A pending interrupt request is accepted when it is enabled.
Fig. 12-10 shows the algorithm for accepting interrupt requests.
When a maskable interrupt request is accepted, the contents of the PSW and PC are saved in the stack in the stated
order, the IE flag is reset to 0 (interrupt disabled state), the content of the priority specification flag corresponding
to the accepted interrupt request is transferred to the ISP. Moreover, the PC is loaded with the contents of the vector
table corresponding to the accepted interrupt request, thus causing a branch. The RETI instruction is used to return
from the interrupt.
order, the IE flag is reset to 0 (interrupt disabled state), the content of the priority specification flag corresponding
to the accepted interrupt request is transferred to the ISP. Moreover, the PC is loaded with the contents of the vector
table corresponding to the accepted interrupt request, thus causing a branch. The RETI instruction is used to return
from the interrupt.
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