Motorola TMS320C6711D Manuale Utente
SPRS292 − OCTOBER 2005
94
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 47)
NO.
GDPA−167
ZDPA−167
−200
−250
−250
UNIT
MIN
MAX
1
tsu(FRH-CKSH) Setup time, FSR high before CLKS high
4
ns
2
th(CKSH-FRH)
Hold time, FSR high after CLKS high
4
ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 47. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0
†‡
(see Figure 48)
NO.
GDPA−167
ZDPA−167
−200
−250
−250
UNIT
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
12
2 − 6P
ns
5
th(CKXL-DRV)
Hold time, DR valid after CLKX low
4
5 + 12P
ns
† P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.