Texas Instruments TMS320DM643 Manuale Utente
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2.4.3
Activation (ACTV)
DDR_CLK
DDR_CKE
DDR_CS
DDR_RAS
DDR_WE
DDR_BA[2:0]
DDR_DQM[3:0]
ACTV
DDR_A[12:0]
DDR_CAS
BANK
ROW
DDR_CLK
Peripheral Architecture
The DDR2 memory controller automatically issues the activate (ACTV) command before a read or write to
a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or
writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects
the row. When the DDR2 memory controller issues an ACTV command, a delay of t
a closed row of memory. The ACTV command opens a row of memory, allowing future accesses (reads or
writes) with minimum latency. The value of DDR_BA[2:0] selects the bank and the value of A[12:0] selects
the row. When the DDR2 memory controller issues an ACTV command, a delay of t
RCD
is incurred before
a read or write command is issued.
shows an example of an ACTV command. Reads or writes to
the currently active row and bank of memory can achieve much higher throughput than reads or writes to
random areas because every time a new row is accessed, the ACTV command must be issued and a
delay of t
random areas because every time a new row is accessed, the ACTV command must be issued and a
delay of t
RCD
incurred.
Figure 7. ACTV Command
DDR2 Memory Controller
16
SPRU986B – November 2007