Fujitsu FR81S Manuale Utente
CHAPTER 36: EXTERNAL BUS INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
[bit5, bit4] ACS[1:0] (A00 to A21 to CSnX delay cycle) : A00 to A21 to CSnX Delay Cycle Count
ACS[1:0] sets the number of delay cycles from outputting A00 to A21 and ASX to outputting CSnX. This
is used when the address for CSnX assert needs to be setup for a fixed time, or when CSnX edges are
required when accessing the same chip select area in sequence.
ACS[1:0]
A00 to A21 → CSnX delay cycle count
00
0 cycle (AWR0 Initial value)
01
1 cycle
10
2 cycles
11
3 cycles
[bit3] ASCY (ASX CYcle) : ASX Output Extension Cycle Count
ASCY sets the number of cycles to extend ASX output. ASX outputs a minimum of 1 cycle.
ASCY
ASX output extension delay cycle count
0
0 cycle (AWR0 Initial value)
1
1 cycle
[bit2] Reserved
Always write "0" to this bit.
[bit1] RDYE (RDY Enable) : RDY Enable
RDYE sets whether the wait insertion function by external RDY pin is enabled or disabled.
RDYE
RDY pin enable
0
Wait insertion by RDY pin disabled (AWR0 initial value)
1
Wait insertion by RDY pin enabled
[bit0] Reserved
Always write "0" to this bit.
MB91520 Series
MN705-00010-1v0-E
1215