Fujitsu FR81S Manuale Utente
CHAPTER 37: BUS PERFORMANCE COUNTERS
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BUS PERFORMANCE COUNTERS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
18
5.3. Operation
This section explains the operation.
Once operation has been enabled by setting the control register, each of the measurement target operations
continues to be counted while the on-chip bus is operating. However, the count is paused in the circumstances
shown below.
⋅
While in emulator mode
The count operation when each of the low-power consumption modes is set is as follows.
⋅
CPU sleep mode
Each measurement target operation is counted.
⋅
Bus sleep mode
Only counted during DMA transfers that operate the on-chip bus. During other periods, counting is not
performed because the measurement target operations do not occur.
⋅
Standby mode (watch mode / stop mode)
Counting is not performed because the measurement target operations do not occur.
The control register is initialized when a reset occurs. Counting is not performed after a reset occurs.
MB91520 Series
MN705-00010-1v0-E
1267