Fujitsu FR81S Manuale Utente
CHAPTER 39: RAMECC
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : RAMECC
FUJITSU SEMICONDUCTOR CONFIDENTIAL
15
4.8. ECC Error Control Register BACKUP-RAM : EECSRA
The bit configuration of the ECC error control register BACKUP-RAM is shown.
During the ECC check of Backup-RAM, this register maintains the status that indicates whether or not the
single-bit error correction or the double-bit error detection has been performed and specifies whether or not
to enable interrupts by such events.
EECSRA : Address 3004
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
DEIE
DEI
Reserved Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R0,W0
R0,W0
R0,W0
R/W
R(RM1),W R/W0
R(RM1),
W0
[bit7 to bit4] Reserved
Always write "0" to these bits
[bit3] DEIE : Double-bit error factor interrupt enable bit
DEIE
Function
0
Disables interrupts.
1
Enables interrupts.
[bit2] DEI : Double-bit error occurrence bit
DEI
Read
Write
0
Double-bit error has not occurred.
Clears this bit.
1
Double-bit error has occurred.
No effect.
[bit1,bit0] Reserved
Always write "0" to these bits.
MB91520 Series
MN705-00010-1v0-E
1306