Fujitsu FR81S Manuale Utente
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
6. Operation of CSIO
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
186
6.1.5.
Interrupts When Using Transmission FIFO and
Flag Setting Timing
Flag Setting Timing
When the transmission FIFO is used, an interrupt generation when the storage data value of the
transmission FIFO is FTICR register (FTICR) setting value or less.
⋅
When the storage data value of the transmission FIFO is FTICR register (FTICR) setting value or less,
the FIFO transmission data request bit (FCR1:FDRQ) will be set to "1". If FIFO transmission interrupt is
enabled (FCR1:FTIE="1") at this time, a transmission interrupt will occur.
⋅
When required data is written to the transmission FIFO after the occurrence of a transmission interrupt,
write "0" to the FIFO transmission data request bit (FCR1:FDRQ) to clear the interrupt request.
⋅
When the transmission FIFO is full, the FIFO transmission data request bit (FCR1:FDRQ) is set to "0".
⋅
The presence of data in the transmission FIFO can be checked by reading the FIFO byte register
(FBYTE) or the transmission FIFO interrupt control register (FTICR).
When FBYTE=0x00 and FTICR=0x00, there is no data in the transmission FIFO.
Figure 6-4 Timing of Interrupt Generation
FIFOBYTE
display
FDRQ
TDRE
TXE
SCK
Transmission
data
Writing to
transmission
FIFO
Clearing by "0" writing
Generation of transmission interrupt *1
Empty transmission buffer *2
*1: FDRQ=1 is set because transmission FIFO is empty.
*2: TDRE=1 is set because there is no data in the transmission buffer register.
*2: TDRE=1 is set because there is no data in the transmission buffer register.
Firstbyte
Secondbyte
Thirdbyte
Fourth byte
0
1
0
0
1
1
2
MB91520 Series
MN705-00010-1v0-E
1499