Fujitsu FR81S Manuale Utente
CHAPTER 41: CAN
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: CAN
FUJITSU SEMICONDUCTOR CONFIDENTIAL
33
[bit0] Data B : Data 4 to 7 update bit
Data B
Function
0
Indicates not updating Data 4 to 7 of message object*1.
[Initial value]
1
Indicates updating Data 4 to 7 of message object*1.
*1: See "4.4 Message Object".
Notes:
⋅
When the TxRqst/NewDat bit of the IFx command mask register (IFxCMSK) is set to "1", the TxRqst
bit settings of the IFx message control register (IFxMCTR) becomes invalid.
⋅
The register becomes invalid in the test basic mode.
(2) When the transfer direction is read (WR/RD="0")
[bit6] Mask : Mask data update bit
Mask
Function
0
Indicates not transferring data (ID mask +MDir + MXtd) from message object*1 to IFx
mask registers 1, 2 (IFxMSK1, IFxMSK2).
[Initial value]
1
Indicates transferring data (ID mask +MDir + MXtd) from message object*1 to IFx
mask registers 1, 2 (IFxMSK1, IFxMSK2) .
[bit5] Arb : Arbitration data update bit
Arb
Function
0
Indicates not transferring data (ID + Dir + Xtd + MsgVal) from message object*1 to IFx
arbitration 1, 2 (IFxARB1, IFxARB2). [Initial value]
1
Indicates transferring data (ID + Dir + Xtd + MsgVal) from message object*1 to IFx
arbitration 1, 2 (IFxARB1, IFxARB2) .
[bit4] Control : Control data update bit
Control
Function
0
Indicates not transferring data from message object*1 to IFx message control register
(IFxMCTR). [Initial value]
1
Indicates transferring data from message object*1 to IFx message control register
(IFxMCTR).
[bit3] CIP : Interrupt clear bit
CIP
Function
0
Indicates holding the IntPnd bit of message object*1 and CAN interrupt pending
register (INTPND). [Initial value]
1
Indicates clearing the IntPnd bit of message object*1 and CAN interrupt pending
register (INTPND) to "0".
MB91520 Series
MN705-00010-1v0-E
1726