Fujitsu FR81S Manuale Utente
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
12
4.5. TPU Timer Interrupt Request Register : TPUTIR
The bit configuration of TPU timer interrupt request register is shown below.
TPUTIR : Address 090C
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IR[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
This register indicates interrupt request status from each timer in TPU . This register is read only. Writing to
the register cause no influence in operation.
[bit7 to bit0] IR[7:0] (Interrupt Request) : Interrupt request
These bits indicate presence of the interrupt request for each channel. These bits show that there is the
interrupt request factor regardless of timer interruption enable register (TPUTIE). And it is possible to use it
as an actual interrupt request, when TPUTIE requests an effective channel.
Bit 0-7 corresponds to channel 0-7 respectively.
IRn
Interrupt Request
0
Ch.n no Interrupt request
1
Ch.n Interrupt request
(N = 0 to 7)
MB91520 Series
MN705-00010-1v0-E
2179