Fujitsu FR81S Manuale Utente
CHAPTER 16: INTERRUPT REQUEST BATCH READ
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : INTERRUPT REQUEST BATCH READ
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
4.24. Interrupt Request Batch Read Register 12
lower-order : IRPR12L (Interrupt Request Peripheral
Read register 12L)
Read register 12L)
The bit configuration of the interrupt request batch read register 12 lower-order is explained.
This register indicates the peripheral that has issued the interrupt request. (Interrupt vector number #59)
IRPR12L : Address 0431
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved Reserved Reserved Reserved OCUIR8 OCUIR9
Reserved
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R,WX
R,WX
R0,WX
R0,WX
[bit3] OCUIR8 (OCU Interrupt Request 8) : Output Compare ch.8 Interrupt Request
[bit2] OCUIR9 (OCU Interrupt Request 9) : Output Compare ch.9 Interrupt Request
Read value of each bit
Meaning
0
No interrupt request has been issued.
1
An interrupt request has been issued.
MB91520 Series
MN705-00010-1v0-E
534