Fujitsu FR81S Manuale Utente
CHAPTER 17: PPG
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
61
Setting and operation procedure:
(1) Writing of PHCSR/PLCSR (High/Low format cycle values)
(2) Writing of PHDUT/PLDUT (High/Low format duty value)
(3) Writing of PCMDWD (PPG communication mode data width)
(4) Writing of PCMDDT (PPG communication mode data)
(5) Enabling of PPG communication mode
(6) Transmitting PCMDDT (PPG communication mode data) to the shifter
(7) Activation trigger generation
(8) Loading of the cycle value to the down count value (PTMR) and the duty value (Which the cycle and
duty of the High or Low format is loaded by PCMDDT, PCMDWD, and CMDSEL is decided)
(9) Counter decrement
(10) The down counter matches the duty value
(11) Output level inversion at the PPG pin
(12) Counter decrement
(13) Counter borrow occurrence
(14) Clearing of PPG pin output level (restoration to normal state)
(15) Reloading of the cycle value to the down count value (PTMR) and the duty value
(16) Repetition of steps (9) to (15) according to the setting of PCMDDT and PCMDWD
(17) PPG communication mode disable (internal circuit and flag register clear)
(18) Resetting all of (1) to (7), Repetition of steps (8) to (15) according to the setting of PCMDDT and
PCMDWD
(19) Operation sequence completion
*: There is no restriction by the order of setting above-mentioned (1) to (5). However, the PPG
communication operation does not start if the setting is not written all of (1) to (5).
*: The PPG communication does not start when the activation trigger is generated without completing the
setting of above-mentioned (1) to (5).
Moreover, in this case, it is necessary to set (1) to (5) again to clear the setting once.
MB91520 Series
MN705-00010-1v0-E
602