Fujitsu FR81S Manuale Utente
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.3.3. Duty Setting Registers 0, 1 : BTxPDUT (Base Timer
0/1 Pulse DuTy register)
The bit configuration of duty setting registers 0, 1 (BTxPDUT) is shown below.
These registers with a buffer set the duty for the 16-bit PWM timer. When the 16-bit down counter value
matches the value set to these registers, the level of the output signal (TOUT) is inverted.
Notes:
⋅
These registers must be accessed in 16-bit mode.
⋅
Set these registers after selecting a base timer function to the 16-bit PWM timer using the FMD2 to
FMD0 bits of the timer control register (BTxTMCR).
⋅
Do not set the value higher than the value set to the cycle setting register (BTxPCSR) when these
registers are rewritten.
⋅
These registers will also be initialized when reset mode is set (writing of BTxTMCR:FMD = 000).
BTxPDUT : Address Base_addr + 0A
H
(Access: Half-word)
bit15
bit14
- - -
bit2
bt1
bit0
D[15:0]
Initial value
0
0
- - -
0
0
0
Attribute R/W
R/W
- - -
R/W
R/W
R/W
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers with a buffer set the duty for the 16-bit PWM timer. When the 16-bit down counter value
matches the value set to these registers, the level of the output signal (TOUT) is inverted.
These registers have a buffer and thus can be rewritten during counting.
If the 16-bit down counter underflows, the buffer value will be transferred.
When the same value is set to these registers and the base timer x cycle setting register (BTxPCSR), the level
of the output signal (TOUT) can be fixed. The output signal level is as follows according to the setting of the
OSEL bit of the base timer x timer control register (BTxTMCR):
⋅
OSEL=0: All "H" level
⋅
OSEL=1: All "L" level
MB91520 Series
MN705-00010-1v0-E
662