Fujitsu FR81S Manuale Utente
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
4.16. SSCG Configuration Setting Register 0 : CCSSCCR0
(CCtl SSCg Config. Register 0)
The bit configuration of the SSCG configuration setting register 0 is shown.
SSCG is variously set.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0")
CCSSCCR0: Address 0529
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
SFREQ[1:0]
SMODE
SSEN
Initial value
0
0
0
1
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
R/W
R/W
[bit7 to bit5] (Reserved)
[bit4] (Reserved)
Always write "1" to this bit.
[bit3, bit2] SFREQ[1:0] (Spread spectrum modulation FREQuency settings) : Spread spectrum
modulation frequency settings
The spread spectrum modulation frequency of SSCG is set.
SFREQ[1:0]
Modulation frequency
00
1/1024
01
1/2048
1x
1/4096
[bit1] SMODE (Spread spectrum modulation MODE settings) : Spread spectrum modulation mode
settings
Sets spread spectrum modulation mode of SSCG.
SMODE
Modulation mode
0
Down Spread
1
Center Spread
Down Spread
time
Target
Period
modulation rate
1/Modulation frequency
Cycle to cycle jitter
MB91520 Series
MN705-00010-1v0-E
196