Fujitsu FR81S Manuale Utente
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
61
5.5.2. Operation in Reload Mode
This section explains the operation in reload mode.
This section explains the operation in reload mode.
Overview
In this mode, the value set in the base timer x cycle setting register (BTxPCSR) is reloaded every time an
underflow occurs to ensure that countdown is continued. To use this mode, set reload mode by resetting the
MDSE bit of the base timer x timer control register (BTxTMCR) to "0"(MDSE=0).
Operation
Activation
Activate the 16-bit PWM timer with the following procedure:
1. Permit the 16-bit PWM timer operation by setting the CTEN bit of the base timer x timer control
register (BTxTMCR) to "1"(CTEN=1).
The 16-bit PWM timer begins to wait for an activation trigger.
2. Enter an activation trigger by one of the following methods:
⋅
Set the STRG bit of the base timer x timer control register (BTxTMCR) to "1" (software trigger).
⋅
Enter an effective edge (an edge set in the EGS1 and EGS0 bits) for an external activation trigger (TGIN
signal).
The 16-bit down counter starts decreasing from the value set in the base timer x cycle setting register
(BTxPCSR).
Notes:
⋅
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified
by the I/O selection register (BTSEL01).
⋅
After a 16-bit PWM timer activation trigger is detected, the following time is required before the value
set in the base timer x cycle setting register (BTxPCSR) can be loaded to the 16-bit down counter:
⋅
If a software trigger is input: 1T (T: Count clock cycle)
⋅
If an external event trigger is used: 2T to 3T (T:Count clock cycle)
Counting Operation
When an activation trigger is input, the 16-bit down counter, in synchronization with the count clock, starts
decreasing from the value set in the cycle setting register (BTxPCSR).
When the value of the 16-bit down counter matches the value of the duty setting register (BTxPDUT), the
operation is performed as follows:
⋅
The DTIR bit of the status control register (BTxSTC) changes to "1".
⋅
The level of the output signal (TOUT) is inverted.
⋅
Countdown is continued. Later, when the 16-bit down counter underflows, the operation is performed as
follows:
⋅
The UDIR bit of the status control register (BTxSTC) changes to "1" and the level of the output signal
(TOUT) is inverted.
⋅
The value of the cycle setting register (BTxPCSR) is reloaded to continue countdown.
Every time an underflow occurs, the value of the cycle setting register (BTxPCSR) is reloaded to continue
counting. Operation to be performed when an activation trigger is input during counting depends on whether
reactivation is permitted based on the RTGEN bit of the timer control register (BTxTMCR).
MB91520 Series
MN705-00010-1v0-E
694