Fujitsu FR81S Manuale Utente
CHAPTER 21: 32-BIT FREE-RUN TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
4.1.3. Compare Clear Register : CPCLR
The bit configuration of the compare clear register is shown.
Compare clear register is a 32-bit register to be used for comparison with the free-run timer.
CPCLR3-5 (Free-run timer 3-5): Address Base_Addr+00
H
(Access: Word)
bit
31
0
CL[31:0]
Initial value 1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
Attribute
R,W
[bit31 to bit0] CL[31:0] : Compare clear
⋅
The compare clear register is used for comparison with the count value of the 32-bit free-run timer. If the
count value of this register matches that of the free-run timer, the 32-bit free-run timer will be reset to
"00000000
H
" and an interrupt will be generated when the value set to this register matches the counter
value. However, the value needs to be written while the timer is inactive (the STOP bit of timer state
control register lower (TCCSL) = "1").
⋅
Writing to this register during operation will have no meaning.
⋅
When accessing this register, use a word access instruction.
MB91520 Series
MN705-00010-1v0-E
811