Lucent Technologies MN102F75K Manuale Utente

C Bus Controller

C Bus Interface Registers

Panasonic Semiconductor Development Company

MN102H75K/F75K/85K/F85K LSI User Manual

306

Panasonic

I2CCLK: I

C Clock Control Register

x’007E46’

To conform to the specification,

the clock signal must be

between 0 and 100 kHz. To sat-
isfy this requirement, always set

I2CCLK to x’032’ or higher.

C[9:0]: Output clock frequency select

This 10-bit field determines the SCL output. With a 12-MHz system clock,
calculate the frequency as follows:

In this case, the following settings apply:

x’032’: 100 kHz

x’06E’: 50 kHz

x’039’: 89.6 kHz

x’08C’: 40 kHz

x’041’: 80 kHz

x’0BE’: 30 kHz

x’04C’: 69.8 kHz

x’122’: 20 kHz

x’05A’: 60 kHz

x’24E’: 10 kHz

I2CBRST: I

C Bus Reset Register

x’007E48’

BRST: Bus reset

When a serious bus error occurs, this bit can be set to 0, forcing the clock
line low and resetting the I

C bus. This function works in all I

C modes.

After a forced reset, the microcontroller is in slave receiver mode. This reset
does not change the contents of the I2CMYAD and I2CCLK registers.

0: Force bus to reset
1: Steady state

I2CBSTS: I

C Bus Status Register

x’007E4A’

I2CBSTS is a two-bit, read-only register that monitors the status of the I

bus.

SDAS: SDA data line status

This bit monitors the state of the I

C data line, SDA.

SCLS: SCL clock line status

This bit monitors the state of the I

C clock line, SCL.

Bit:

—

Reset:

R/W:

R/W

Bit:

—

BRST

Reset:

R/W:

R/W

Bit:

—

SDAS

SCLS

Reset:

R/W:

SC L

12 MHz

(

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