FIC M296 Manuale Utente
Hardware Functional Overview
data w/ 533 MB/s from/to memory sub-system to/from the Multi-threaded I/O Link Packet
Layer in SiS962L.
Layer in SiS962L.
The SiS645DX functions and capabilities include:
PC2001 Compliance
High Performance Host Interface
. Support Intel Pentium 4 series CPU with data transfer rate of 400MHz and Over
Clocking up to 533MHz.
. Support 12 Outstanding Transactions
. Synchronous/Asynchronous Host-t-DRAM Timing
. Master deliver System Bus Interrupt support
. Smart Pre-fetch mechanism to boost memory read performance
. Support 2M/4M/8M/16M TSEG SMRAM
. Support Defer function to maximize bus utilization
. Support Dynamic Bus Inversion
. AGTL+ & AGTL compliant bus driver auto compensation
Clocking up to 533MHz.
. Support 12 Outstanding Transactions
. Synchronous/Asynchronous Host-t-DRAM Timing
. Master deliver System Bus Interrupt support
. Smart Pre-fetch mechanism to boost memory read performance
. Support 2M/4M/8M/16M TSEG SMRAM
. Support Defer function to maximize bus utilization
. Support Dynamic Bus Inversion
. AGTL+ & AGTL compliant bus driver auto compensation
64 Bit High Performance DDR333/DDR266/PC133 Memory Controlle
r
.
Supports DDR333/DDR266/DDR200 SDRAM or PC133/100 SDRAM
. Support Up to 2 un-buffer DIMM DDR333 or up to 3 un-buffer Double-sided DIMM
DDR266/200
. Up to 1 GB per DIMM with max. memory size up to 3 GB
. Supports 16Mb, 64Mb, 128Mb, 256Mb, & 512Mb SDRAM technology with page
size from 2KB up to 16 KB
. Sustains DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
. Programmable buffer strength optimizing performance and stability
. Dynamic Clock Enable(CKE) control placing the SDRAM into Suspend to DRAM
state
. High performance unified memory controller optimizing the DRAM bus utilization
. 128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
DDR266/200
. Up to 1 GB per DIMM with max. memory size up to 3 GB
. Supports 16Mb, 64Mb, 128Mb, 256Mb, & 512Mb SDRAM technology with page
size from 2KB up to 16 KB
. Sustains DDR SDRAM CAS Latency at options of 2, 2.5, & 3 clocks
. Programmable buffer strength optimizing performance and stability
. Dynamic Clock Enable(CKE) control placing the SDRAM into Suspend to DRAM
state
. High performance unified memory controller optimizing the DRAM bus utilization
. 128KB SMRAM space re-mapping to A0000h, B0000h, or E0000h
Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
. AGP v2.0 Compliant
. Supports Graphic Window Size from 4MBytes to 256MBytes
. Supports Pipelined Process in CPU-to- A.G.P. Access
. Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P.
Controller Read/Write Performance
. Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to
A.G.P. device
. Supports AGP 4X/2X Interface w/ Fast Write Transaction
. Supports Graphic Window Size from 4MBytes to 256MBytes
. Supports Pipelined Process in CPU-to- A.G.P. Access
. Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance A.G.P.
Controller Read/Write Performance
. Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to
A.G.P. device
. Supports AGP 4X/2X Interface w/ Fast Write Transaction
HighThroughput SiS MuTIOL connect to SiS962L MuTIOL Media I/O
4-10
FIC M295 / M296 Service Manual