NEC PD78055 Manuale Utente
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CHAPTER 19 SERIAL INTERFACE CHANNEL 2
19.4.4 Limitations when UART mode is used
In the UART mode, the reception completion interrupt request (INTSR) occurs a certain time after the reception
error interrupt request (INTSER) has occurred and then cleared. Consequently, the following phenomenon may occur.
•
Description
If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the reception completion
interrupt request (INTSR) does not occur on occurrence of a reception error. If the receive buffer register (RXB)
is read at certain timing (a in Figure 19-14) during the reception error interrupt (INTSER) processing, the internal
error flag is cleared to 0. As a result, it is judged that no reception error has occurred, and INTSR, which must
not occur, occurs. Figure 19-14 illustrates this operation.
Figure 19-14. Reception Completion Interrupt Request Generation Timing (when ISRM = 1)
Remark
ISRM : Bit 1 of asynchronous serial interface mode register (ASIM)
f
SCK
: Source clock of 5-bit counter of baud rate generator
RXB : Receive buffer register
To avoid this phenomenon, take the following measures:
•
Countermeasures
• In case of framing error or overrun error
Disable the receive buffer register (RXB) from being read for a certain time (T2 in Figure 19-15) after the
reception error interrupt request (INTSER) has occurred.
It is judged that reception error has not
occurred, and INTSR occurs
occurred, and INTSR occurs
Reading RXB
Cleared on
reading RXB
a
f
sck
INTSER (when framing/
overrun error occurs)
Error flag
(internal flag)
INTSR
Interrupt routine of CPU