Jameco Electronics 3000 Manuale Utente
User’s Manual
219
Figure 16-3. Memory Read and Write Cycles—Early
Output Enable and Write Enable Timing
Tadr
Tadr
Memory Read (no wait states)
CLK
A[19:0]
Memory Write (no extra wait states)
CLK
A[19:0]
valid
T1
T2
T1
Tw
T2
valid
TOEx
TOEx
D[7:0]
valid
Thold
Tsetup
/CSx
/OEx
TCSx
TCSx
valid
D[7:0]
TDHZV
TDVHZ
/CSx
/WEx
TCSx
TCSx
TWEx
TWEx