Motorola MC68VZ328 Manuale Utente
7-8
MC68VZ328 User’s Manual
DRAM Controller Operation
7.2.4
LCD Interface
Figure 7-2 illustrates the LCD controller and DRAM controller interface. The DRAM controller supports
page bursting accesses. When the PAGE_ACCESS signal is active and CSD[1:0] is active, Fast Page
Mode or EDO RAM mode will be initiated.
page bursting accesses. When the PAGE_ACCESS signal is active and CSD[1:0] is active, Fast Page
Mode or EDO RAM mode will be initiated.
In Fast Page Mode mode, the first access will always be 4 clocks. Additional clocks may be added to the
access cycle for the second and subsequent access cycles using the BC0 and BC1 bits of the DRAMC
register. One, two, three, and four additional clocks are supported by the DRAM controller. The notation
for the additional clock cycles is to display the first three numbers, separated by hyphens, followed by an
ellipsis and the final number: first clock-second clock-third clock-...-last clock. For example, the notation
4-2-2-...-2 represents 4 clocks for the first transfer and 2 clocks for the second and subsequent transfers.
The first access is always 4 clocks.
access cycle for the second and subsequent access cycles using the BC0 and BC1 bits of the DRAMC
register. One, two, three, and four additional clocks are supported by the DRAM controller. The notation
for the additional clock cycles is to display the first three numbers, separated by hyphens, followed by an
ellipsis and the final number: first clock-second clock-third clock-...-last clock. For example, the notation
4-2-2-...-2 represents 4 clocks for the first transfer and 2 clocks for the second and subsequent transfers.
The first access is always 4 clocks.
Single clocks and transfers are only supported in EDO RAM mode, allowing the fastest LCD DMA
transfers. However, in EDO RAM mode, the BC0 and BC1 bits are ignored by the DRAM controller. For
additional information about operation using an LCD display, see Chapter 8, “LCD Controller.”
transfers. However, in EDO RAM mode, the BC0 and BC1 bits are ignored by the DRAM controller. For
additional information about operation using an LCD display, see Chapter 8, “LCD Controller.”
When an LCD controller cycle and a refresh request collide before the LCD controller cycle starts, refresh
will go first, and N more clocks will be added to the first access (N is the number of system clock cycles
required for refresh). Therefore, in EDO RAM mode, for a 4-1-1-...-1 cycle, the access will become
(4+N)-1-1-...-1.
will go first, and N more clocks will be added to the first access (N is the number of system clock cycles
required for refresh). Therefore, in EDO RAM mode, for a 4-1-1-...-1 cycle, the access will become
(4+N)-1-1-...-1.
When consecutive LCD controller burst accesses cross a memory page boundary, the DRAM controller
will hold the LCD controller that is negating the internal DTACK signal to change the row address and
wait for a precharge time. When a refresh request occurs in the middle of an LCD controller cycle transfer,
refresh will be deferred until the end of the LCD controller cycle. Since the LCD controller cycle only lasts
for 8 cycles, the deferred refresh cycle will not overlap with the next refresh request.
will hold the LCD controller that is negating the internal DTACK signal to change the row address and
wait for a precharge time. When a refresh request occurs in the middle of an LCD controller cycle transfer,
refresh will be deferred until the end of the LCD controller cycle. Since the LCD controller cycle only lasts
for 8 cycles, the deferred refresh cycle will not overlap with the next refresh request.
The DTACK signal is used to hold the LCD controller after the address changes on each word of an LCD
transfer. If DTACK is asserted, the LCD controller will assume a fixed wait-state transfer per the setup
within the LCD controller. The LCD controller will hold as long as DTACK is not asserted.
transfer. If DTACK is asserted, the LCD controller will assume a fixed wait-state transfer per the setup
within the LCD controller. The LCD controller will hold as long as DTACK is not asserted.
The PAGE_ACCESS signal from the LCD controller indicates to the DRAM controller and system
integration module that an LCD DMA burst transfer is about to begin. The associated chip-select signal
will hold active throughout the LCD controller’s access cycle. In this mode, the DRAM controller supports
page accesses.
integration module that an LCD DMA burst transfer is about to begin. The associated chip-select signal
will hold active throughout the LCD controller’s access cycle. In this mode, the DRAM controller supports
page accesses.
Figure 7-2. LCD Controller and DRAM Controller Interface
DTACK
LCD
DRAM
Address
Data
MD[12:0]
External
Address
Data
PAGE_ACCESS
External
Controller
Controller