Motorola MC68VZ328 Manuale Utente
7-16
MC68VZ328 User’s Manual
Programming Model
7.3.3
SDRAM Control Register
This register controls operation when SDRAM is being used. The bit position and values are shown in the
following register display. The details about the register settings are described in Table 7-8.
following register display. The details about the register settings are described in Table 7-8.
SDCTRL
SDRAM Control Register
0x(FF)FFFC04
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
SDEN
CPM
RE
IP
MR
SCOL
BNKADDH
BNKADDL
CL
RACL
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0x003C
Table 7-8. SDRAM Control Register Description
Name
Description
Setting
SDEN
Bit 15
Bit 15
SDRAM Enable—When this bit is set, together with
the DRAM enable bit (bit 9 of the CSD register) being
set and the EDO bit (DRAMC register bit 10) being
cleared, the SDRAM operation is enabled.
the DRAM enable bit (bit 9 of the CSD register) being
set and the EDO bit (DRAMC register bit 10) being
cleared, the SDRAM operation is enabled.
0 = SDRAM disable.
1 = SDRAM enable (see description for
1 = SDRAM enable (see description for
other bits that must be set).
CPM
Bit 14
Bit 14
Continuous Page Mode—This bit enables the DRAM
to operate in continuous page mode. DRAM will only
be precharged during a page-miss condition.
to operate in continuous page mode. DRAM will only
be precharged during a page-miss condition.
0 = SDRAM not in continuous page mode.
1 = SDRAM in continuous page mode.
1 = SDRAM in continuous page mode.
Reserved
Bit 13
Bit 13
Reserved
This bit is reserved and must be set to 0.
RE
Bit 12
Bit 12
Refresh Enable—This bit enables the refresh cycle for
SDRAM.
SDRAM.
0 = SDRAM Refresh cycle not enabled.
1 = SDRAM refresh cycle enabled.
1 = SDRAM refresh cycle enabled.
IP
Bit 11
Bit 11
Initiate All Bank Precharge Command—Setting this
bit triggers the precharge command for all banks of
SDRAM.
bit triggers the precharge command for all banks of
SDRAM.
0 = IP command to SDRAM disabled.
1 = IP command to SDRAM enabled.
1 = IP command to SDRAM enabled.
MR
Bit 10
Bit 10
Initiate Mode Register Set Command—Setting this
bit triggers the load mode register command to
SDRAM.
bit triggers the load mode register command to
SDRAM.
0 = MR command to SDRAM disabled.
1 = MR command to SDRAM enabled.
1 = MR command to SDRAM enabled.
Reserved
Bits 9–7
Bits 9–7
Reserved
These bits are reserved and should be set
to 0.
to 0.
SCOL
Bit 6
Bit 6
SDRAM Column Option—This bit selects the SDRAM
column address MD0.
column address MD0.
0 = PA1 (normally for 16-bit SDRAM).
1 = PA0 (normally for 8-bit SDRAM).
1 = PA0 (normally for 8-bit SDRAM).
BNKADDH
Bits 5–4
Bits 5–4
SDRAM High Order Bank Address Line
Selection—A 2-bit bank register selection address is
generated by selecting the appropriate CPU address
line. This register bit allows selection of the high order
bit.
Selection—A 2-bit bank register selection address is
generated by selecting the appropriate CPU address
line. This register bit allows selection of the high order
bit.
00 = PA20.
01 = PA22.
10 = PA24.
11 = Force this bank address line to 0.
01 = PA22.
10 = PA24.
11 = Force this bank address line to 0.
See Table 7-9 on page 7-17 for program-
ming examples.
ming examples.