Motorola MC68VZ328 Manuale Utente

9-7

 

This section describes registers that you may need to configure so that the interrupt controller can properly 
process interrupts, generate vector numbers, and post interrupts to the core.

When programmed as edge-triggered interrupts, all external interrupts
(INT[3:0], IRQ1, IRQ2, IRQ3, and IRQ6) can be cleared by writing a 1 to
the corresponding status bit in the interrupt status register (ISR). When
programmed as level-triggered interrupts, these interrupts are cleared at
the requesting sources. All interrupts from internal peripheral devices are
level-triggered interrupts to the interrupt handler, and they are cleared at
the requesting sources. 

The interrupt vector register (IVR) is used to program the upper 5 bits of the interrupt vector number. 
During the interrupt acknowledge cycle, the lower 3 bits, encoded from the interrupt level, are combined 
with the upper 5 bits to form an 8-bit vector number. The CPU uses the vector number to generate a vector 
address. During system startup, this register should be configured so that the MC68VZ328’s external and 
internal interrupts can be handled properly by their software handlers. If an interrupt occurs before the IVR 
has been programmed, the interrupt vector number 0x0F is returned to the CPU as an uninitialized 
interrupt, which has the interrupt vector 0x3C. 

The register bit assignments are shown in the following register display, and their settings are described in 
Table 9-3.

Interrupt Vector Register

BIT  7

6

5

4

3

2

1

BIT  0

VECTOR

TYPE

rw

rw

rw

rw

rw

RESET

0

0

0

0

0

0

0

0

0x00

VECTOR
Bits 7–3

Vector Number—This field represents the upper 5 bits of the inter-
rupt vector number.

See description.

Reserved
Bits 2–0

Reserved

These bits are reserved 
and should be set to 0.