Motorola MC68VZ328 Manuale Utente
9-16
MC68VZ328 User’s Manual
Programming Model
9.6.5
Interrupt Pending Register
The read-only interrupt pending register (IPR) indicates which interrupts are pending. If an interrupt
source requests an interrupt, but that interrupt is masked by the interrupt mask register, then that interrupt
bit will be set in this register, but not in the interrupt status register. If the pending interrupt is not masked,
the interrupt bit will be set in both registers.
source requests an interrupt, but that interrupt is masked by the interrupt mask register, then that interrupt
bit will be set in this register, but not in the interrupt status register. If the pending interrupt is not masked,
the interrupt bit will be set in both registers.
IPR
Interrupt Pending Register
0x(FF)FFF310
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT
16
EMI
Q
RTI
SPI
1
IRQ
5
IRQ
6
IRQ
3
IRQ
2
IRQ
1
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000000
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
PW
M2
UA
RT
RT
2
INT
3
INT
2
INT
1
INT
0
PW
M1
KB
TM
R2
RT
C
WD
T
UA
RT
RT
1
TM
R1
SPI
2
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00000000
Table 9-7. Interrupt Pending Register Description
Name
Description
Settings
Reserved
Bits 31–24
Bits 31–24
Reserved
These bits are reserved and
should be set to 0.
should be set to 0.
EMIQ
Bit 23
Bit 23
Emulator Interrupt Pending—When set, this bit indicates that the
in-circuit emulation module or EMUIRQ pin is requesting an interrupt
on level 7. This bit can be generated from three interrupt sources:
two breakpoint interrupts from the in-circuit emulation module and an
external interrupt from EMUIRQ, which is an active low, edge-sensi-
tive interrupt. To clear this interrupt, you must read the ICEMSR reg-
ister to identify the interrupt source and write a 1 to the
corresponding bit of that register. See Section 16.2.4, “In-Circuit
Emulation Module Status Register,” on page 16-10 for more informa-
tion.
in-circuit emulation module or EMUIRQ pin is requesting an interrupt
on level 7. This bit can be generated from three interrupt sources:
two breakpoint interrupts from the in-circuit emulation module and an
external interrupt from EMUIRQ, which is an active low, edge-sensi-
tive interrupt. To clear this interrupt, you must read the ICEMSR reg-
ister to identify the interrupt source and write a 1 to the
corresponding bit of that register. See Section 16.2.4, “In-Circuit
Emulation Module Status Register,” on page 16-10 for more informa-
tion.
0 = No emulator interrupt is
pending.
1 = An emulator interrupt is
pending.
RTI
Bit 22
Bit 22
Real-Time Interrupt Pending (Real-Time Clock)—When set, this
bit indicates that the real-time timer interrupt is pending. The fre-
quency can be selected inside the real-time clock module, which can
function as an additional timer.
bit indicates that the real-time timer interrupt is pending. The fre-
quency can be selected inside the real-time clock module, which can
function as an additional timer.
0 = No real-time timer
interrupt is pending.
1 = A real-time timer interrupt
is pending.
SPI1
Bit 21
Bit 21
SPI 1 Interrupt Pending—When set, this bit indicates an interrupt
event from SPI unit 1.
event from SPI unit 1.
0 = No SPI 1 interrupt is
pending.
1 = An SPI 1 interrupt is
pending.