Motorola MC68VZ328 Manuale Utente
10-2
MC68VZ328 User’s Manual
Status of I/O Ports During Reset
10.2
Status of I/O Ports During Reset
Two types of resets affect the states of the MC68VZ328’s I/O ports: warm reset and power-up reset. A
warm reset refers to any reset initiated while power to the processor remains uninterrupted. A power-up
reset occurs the first time power is supplied to the MC68VZ328. Power-up resets are also called cold start
resets.
warm reset refers to any reset initiated while power to the processor remains uninterrupted. A power-up
reset occurs the first time power is supplied to the MC68VZ328. Power-up resets are also called cold start
resets.
10.2.1
Warm Reset
Figure 10-1 on page 10-3 details timing during a warm reset. All I/O ports, except Ports B and M, reset to
their default states on assertion of the reset signal and remain at their default states during the time period
labeled Reset Assertion Time Length. The port default state is determined by the register reset values of
the I/O port registers. Register reset values are found in Table 3-1 on page 3-2 and Table 3-2 on page 3-8.
Ports B and M maintain their previous programmed states on reset assertion and retain their states during
the Reset Assertion Time Length. The previous states of Ports B and M before reset assertion are, for the
purposes of the figure, assumed.
their default states on assertion of the reset signal and remain at their default states during the time period
labeled Reset Assertion Time Length. The port default state is determined by the register reset values of
the I/O port registers. Register reset values are found in Table 3-1 on page 3-2 and Table 3-2 on page 3-8.
Ports B and M maintain their previous programmed states on reset assertion and retain their states during
the Reset Assertion Time Length. The previous states of Ports B and M before reset assertion are, for the
purposes of the figure, assumed.
Table 10-1. Dedicated I/O Functions of Ports
Port
Dedicated I/O Module
Dedicated I/O Module
Dedicated I/O Module
Dedicated I/O Module
A
Lower byte of data bus
B
Chip-select
DRAM controller
GP timers
PWM output
C
LCD controller
D
Interrupt controller
E
SPI DRAM
controller
UART
Bus
control
F
DRAM controller
CGM
Address bits 23–20
Interrupt request 5
LCD contrast
Chip-select
G
Bus control
In-circuit emulation
Address bit 0
J
UART
SPI
K
Bus control
LCD controller
SPI
M
DRAM controller