Motorola MC68VZ328 Manuale Utente

12-9

Each timer compare (TCMPx) register contains the value that is compared with the counter. A compare 
event is generated when the counter matches the value in this register. This register is set to 0xFFFF at 
system reset. The settings for the registers are described in Table 12-4.

Timer Compare Register 1

Timer Compare Register 2

BIT 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BIT 0

COMPARE

TYPE

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

RESET

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0xFFFF

BIT 15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BIT 0

COMPARE

TYPE

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

rw

RESET

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0xFFFF

COMPARE
Bits 15–0

Compare Value—Write this field’s value to 
generate a compare event when the counter 
matches this value.

This field has a valid range 0x0000 to 0xFFFF.