Motorola MC68VZ328 Manuale Utente
13-2
MC68VZ328 User’s Manual
SPI 1 Operation
13.2
SPI 1 Operation
The SPI 1 signal pins are multiplexed with bit 0 (DATA_READY) of the Port K register and bits 3–0
(MOSI, MISO, and SPICLK1) of the Port J register. Therefore, before SPI 1 is used, it is necessary to write
0 to these bits in the PKSEL and PJSEL registers, respectively. See Section 10.4.9.5, “Port J Select
Register,” on page 10-33 and Section 10.4.10.5, “Port K Select Register,” on page 10-36 for detailed
information.
(MOSI, MISO, and SPICLK1) of the Port J register. Therefore, before SPI 1 is used, it is necessary to write
0 to these bits in the PKSEL and PJSEL registers, respectively. See Section 10.4.9.5, “Port J Select
Register,” on page 10-33 and Section 10.4.10.5, “Port K Select Register,” on page 10-36 for detailed
information.
13.2.1
Using SPI 1 as Master
If SPI 1 is configured as master, it uses a serial link to transfer data between the MC68VZ328 and a
peripheral device. A chip-enable signal and a clock signal are used to transfer data between the two
devices. If the external device is a transmit-only device, the SPI master’s output port can be ignored and
used for other purposes. In order to utilize the internal TxD and RxD data FIFOs, two auxiliary output
signals, SS and DATA_READY, are used for data transfer rate control. The user may also program the
sample period control register to a fixed data transfer rate.
peripheral device. A chip-enable signal and a clock signal are used to transfer data between the two
devices. If the external device is a transmit-only device, the SPI master’s output port can be ignored and
used for other purposes. In order to utilize the internal TxD and RxD data FIFOs, two auxiliary output
signals, SS and DATA_READY, are used for data transfer rate control. The user may also program the
sample period control register to a fixed data transfer rate.
13.2.2
Using SPI 1 as Slave
If SPI 1 is configured as slave, the SPI 1 control register can be configured to match the external SPI
master’s timing. SS becomes an input signal and can be used for data latching from and loading to the
internal data shift registers, as well as to increment the data FIFO. Figure 13-2 shows the generic SPI
timing.
master’s timing. SS becomes an input signal and can be used for data latching from and loading to the
internal data shift registers, as well as to increment the data FIFO. Figure 13-2 shows the generic SPI
timing.
Figure 13-2. SPI 1 Generic Timing
NOTE:
SPI 1 does not consume any power when it is disabled.
SPICLK1
MOSI
B
n
...
...
b
1
b
0
SPICLK1
SPICLK1
SPICLK1
(POL=1, PHA=1)
(POL=1, PHA=0)
(POL=0, PHA=1)
(POL=0, PHA=0)
MISO
B
n
...
...
b
1
b
0
B
n-1
B
n-2
B
n-1
B
n-3
B
n-3
B
n-2