Motorola MC68VZ328 Manuale Utente
13-8
MC68VZ328 User’s Manual
SPI 1 Programming Model
13.3.4
SPI 1 Interrupt Control/Status Register
This register is used to provide interrupt control and status of various operations in SPI 1. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-4.
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-4.
SPIINTCS
SPI 1 Interrupt Control/Status Register
0x(FF)FFF706
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
BO
EN
EN
RO
EN
RFE
N
RHE
N
RRE
N
TFE
N
THE
N
TEE
N
B
O
R
O
O
R
F
R
H
H
R
R
R
T
F
F
T
H
TE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 13-4. SPI 1 Interrupt Control/Status Register Description
Name
Description
Setting
BOEN
Bit 15
Bit 15
Bit Count Overflow Interrupt Enable—This bit,
when set, allows an interrupt to be generated
when an overflow bit count condition exists. See
the description of the BO (bit 7) for details.
when set, allows an interrupt to be generated
when an overflow bit count condition exists. See
the description of the BO (bit 7) for details.
0 = Disable bit count overflow interrupt.
1 = Enable bit count overflow interrupt.
1 = Enable bit count overflow interrupt.
ROEN
Bit 14
Bit 14
RxFIFO Overflow Interrupt Enable—This bit,
when set, allows an interrupt to be generated
when an overflow occurs in the RxFIFO. See the
description of the RO (bit 6) for details.
when set, allows an interrupt to be generated
when an overflow occurs in the RxFIFO. See the
description of the RO (bit 6) for details.
0 = Disable RxFIFO overflow interrupt.
1 = Enable RxFIFO overflow interrupt.
1 = Enable RxFIFO overflow interrupt.
RFEN
Bit 13
Bit 13
RxFIFO Full Interrupt Enable—This bit, when
set, allows an interrupt to be generated when
there are 8 data words in the RxFIFO. See the
description of the RF (bit 5) for details.
set, allows an interrupt to be generated when
there are 8 data words in the RxFIFO. See the
description of the RF (bit 5) for details.
0 = Disable RxFIFO full interrupt enable.
1 = Enable RxFIFO full interrupt enable.
1 = Enable RxFIFO full interrupt enable.
RHEN
Bit 12
Bit 12
RxFIFO Half Interrupt Enable—This bit, when
set, allows an interrupt to be generated when the
contents of the RxFIFO is more than or equal to
4 data words. See the description of the RH (bit
4) for details.
set, allows an interrupt to be generated when the
contents of the RxFIFO is more than or equal to
4 data words. See the description of the RH (bit
4) for details.
0 = Disable half interrupt enable.
1 = Enable half interrupt enable.
1 = Enable half interrupt enable.
RREN
Bit 11
Bit 11
RxFIFO Data Ready Interrupt Enable—This
bit, when set, allows an interrupt to be generated
when at least 1 data word is ready in the
RxFIFO. See the description of the RR (bit 3) for
details.
bit, when set, allows an interrupt to be generated
when at least 1 data word is ready in the
RxFIFO. See the description of the RR (bit 3) for
details.
0 = Disable data ready interrupt enable.
1 = Enabled data ready interrupt enable.
1 = Enabled data ready interrupt enable.
TFEN
Bit 10
Bit 10
TxFIFO Full Interrupt Enable—This bit, when
set, causes an interrupt to be generated when
the TxFIFO buffer is full and the RFEN bit is set.
set, causes an interrupt to be generated when
the TxFIFO buffer is full and the RFEN bit is set.
0 = Disable TxFIFO full interrupt.
1 = Enable TxFIFO full interrupt.
1 = Enable TxFIFO full interrupt.
THEN
Bit 9
Bit 9
TxFIFO Half Interrupt Enable—This bit, when
set, causes an interrupt to be generated when
the TxFIFO buffer is half empty and the THEN
bit is set.
set, causes an interrupt to be generated when
the TxFIFO buffer is half empty and the THEN
bit is set.
0 = Disable TxFIFO half interrupt.
1 = Enable TxFIFO half interrupt.
1 = Enable TxFIFO half interrupt.