Motorola MC68VZ328 Manuale Utente
13-12
MC68VZ328 User’s Manual
SPI 2 Operation
13.5
SPI 2 Operation
The serial peripheral interface 2 operates as a master-mode-only SPI module using a serial link to transfer
data between the MC68VZ328 and a peripheral device. A chip-enable signal and a clock signal are used to
transfer data between the two devices. If the external device is a transmit-only device, SPI 2’s output port
is freed to be used for other purposes. See Figure 13-4.
data between the MC68VZ328 and a peripheral device. A chip-enable signal and a clock signal are used to
transfer data between the two devices. If the external device is a transmit-only device, SPI 2’s output port
is freed to be used for other purposes. See Figure 13-4.
Figure 13-4. SPI 2 Generic Timing
The SPI 2 pins are multiplexed with bits 2–0 of the Port E registers, so when you use SPI 2, you must write
000 to these bits in the PESEL register. See Section 10.4.6, “Port E Registers,” on page 10-21 for more
information.
000 to these bits in the PESEL register. See Section 10.4.6, “Port E Registers,” on page 10-21 for more
information.
NOTE:
The SPI 2 module does not consume any power when it is disabled.
You must enable the ENABLE bit in the SPICONT2 register before you can change any other bits. To
perform a serial data transfer, set the ENABLE bit; then, in a separate write cycle, set the appropriate
control bits. The SPI 2 module is then ready to accept data into the SPIDATA2 register, which cannot be
written while the SPI 2 module is disabled or busy. Once the data is loaded, the XCH bit is set in the
SPICONT2 register, which triggers an exchange. The XCH bit remains set until the transfer is complete. If
you clear the MSPI bit in the interrupt mask register before you trigger an exchange, an interrupt will be
posted when the exchange is complete. See Section 9.6.3, “Interrupt Mask Register,” on page 9-10 for
more information. You can discover the status of the interrupt in the IRQ bit of the SPICONT2 register,
and you can clear this bit by writing a 0 to it.
perform a serial data transfer, set the ENABLE bit; then, in a separate write cycle, set the appropriate
control bits. The SPI 2 module is then ready to accept data into the SPIDATA2 register, which cannot be
written while the SPI 2 module is disabled or busy. Once the data is loaded, the XCH bit is set in the
SPICONT2 register, which triggers an exchange. The XCH bit remains set until the transfer is complete. If
you clear the MSPI bit in the interrupt mask register before you trigger an exchange, an interrupt will be
posted when the exchange is complete. See Section 9.6.3, “Interrupt Mask Register,” on page 9-10 for
more information. You can discover the status of the interrupt in the IRQ bit of the SPICONT2 register,
and you can clear this bit by writing a 0 to it.
For systems that need more than 16 clocks to transfer data, the ENABLE bit can remain asserted between
exchanges. The enable signal required by some SPI slave devices should be provided by an I/O port pin.
exchanges. The enable signal required by some SPI slave devices should be provided by an I/O port pin.
SPICLK2
SPIRXD
B
n
...
...
b
1
b
0
SPICLK2
SPICLK2
SPICLK2
(POL=1, PHA=1)
(POL=1, PHA=0)
(POL=0, PHA=1)
(POL=0, PHA=0)
SPITXD
B
n
...
...
b
1
b
0
B
n-1
B
n-2
B
n-1
B
n-3
B
n-3
B
n-2