Motorola MC68VZ328 Manuale Utente
UART Operation
Universal Asynchronous Receiver/Transmitter 1 and 2
14-5
If the driver software has excessive interrupt service latency time, use the FIFO HALF interrupt. With
UART 1, the transmitter generates an interrupt when the FIFO has fewer than 4 bytes remaining. Because
UART 2 has a larger FIFO buffer, the transmitter generates an interrupt when the FIFO has a number of
empty slots that is less than or equal to the number specified by the TxFIFO level marker of the FIFO level
marker interrupt register.
UART 1, the transmitter generates an interrupt when the FIFO has fewer than 4 bytes remaining. Because
UART 2 has a larger FIFO buffer, the transmitter generates an interrupt when the FIFO has a number of
empty slots that is less than or equal to the number specified by the TxFIFO level marker of the FIFO level
marker interrupt register.
If the FIFO buffer is not needed, only the TX AVAIL interrupt is required. This interrupt is generated
when at least one space is available in the FIFO. Any data that is written to the FIFO while the TX AVAIL
bit is clear is ignored.
when at least one space is available in the FIFO. Any data that is written to the FIFO while the TX AVAIL
bit is clear is ignored.
14.3.1.2
CTS Signal Operation
CTSx is used for hardware flow control. If CTSx is negated (high), the transmitter finishes sending the
character in progress (if any) and then waits for CTSx to become asserted (low) again before starting the
next character. The current state of the CTSx pin is sampled by the bit clock and can be monitored by
reading the CTSx STAT bit of the UTX register. An interrupt can be generated when the CTSx pin
changes state. The CTSx DELTA bit of the UTX register goes high when the CTSx pin toggles. For
applications that do not need hardware flow control, such as IrDA, the NOCTSx bit of the UTX register
should be set. While this bit is set, characters will be sent as soon as they are available in the FIFO. Parity
errors can be generated for debugging purposes by setting the FORCE PERR bit in the corresponding
UMISC register.
character in progress (if any) and then waits for CTSx to become asserted (low) again before starting the
next character. The current state of the CTSx pin is sampled by the bit clock and can be monitored by
reading the CTSx STAT bit of the UTX register. An interrupt can be generated when the CTSx pin
changes state. The CTSx DELTA bit of the UTX register goes high when the CTSx pin toggles. For
applications that do not need hardware flow control, such as IrDA, the NOCTSx bit of the UTX register
should be set. While this bit is set, characters will be sent as soon as they are available in the FIFO. Parity
errors can be generated for debugging purposes by setting the FORCE PERR bit in the corresponding
UMISC register.
The SEND BREAK bit of the corresponding UTX register is used to generate a Break character
(continuous zeros). Use the following procedure to send the minimum number of valid Break characters.
(continuous zeros). Use the following procedure to send the minimum number of valid Break characters.
1. Make sure the BUSY bit in the UTX register is set.
2. Wait until the BUSY bit goes low.
3. Clear the TXEN bit in the USTCNT register, which flushes the FIFO.
4. Wait until the BUSY bit goes low.
5. Set the TXEN bit.
6. Set the SEND BREAK bit in the UTX register.
7. Load a dummy character into the FIFO.
8. Wait until the BUSY bit goes low.
9. Clear the SEND BREAK bit.
After the procedure finishes, the FIFO should be empty and the transmitter should be idle and waiting for
the next character.
the next character.
If the TXEN bit of the USTCNT register is negated while a character is being transmitted, the character
will be completed before the transmitter returns to IDLE. The transmit FIFO is immediately flushed when
the TXEN bit is cleared. When the message has been completely sent and the UART is to be disabled,
monitor the BUSY bit to determine when the transmitter has actually completed sending the final
character. Remember that there may be a long time delay, depending on the baud rate. It is safe to clear the
UEN bit of the corresponding USTCNT register after the BUSY bit becomes clear. The BUSY bit can also
be used to determine when to disable the transmitter and turn the link around to receive IrDA applications.
will be completed before the transmitter returns to IDLE. The transmit FIFO is immediately flushed when
the TXEN bit is cleared. When the message has been completely sent and the UART is to be disabled,
monitor the BUSY bit to determine when the transmitter has actually completed sending the final
character. Remember that there may be a long time delay, depending on the baud rate. It is safe to clear the
UEN bit of the corresponding USTCNT register after the BUSY bit becomes clear. The BUSY bit can also
be used to determine when to disable the transmitter and turn the link around to receive IrDA applications.
When IrDA mode is enabled, the transmitter produces a pulse that is less than or equal to three-sixteenths
of bit time for each zero bit sent. Ones are sent as “no pulse.” When the TXPOL bit of the UMISC register
is low, pulses are active high. When the TXPOL bit is high, pulses are active low and idle is high.
of bit time for each zero bit sent. Ones are sent as “no pulse.” When the TXPOL bit of the UMISC register
is low, pulses are active high. When the TXPOL bit is high, pulses are active low and idle is high.