Motorola MC68VZ328 Manuale Utente
14-20
MC68VZ328 User’s Manual
Programming Model
14.4.8
UART 2 Status/Control Register
The UART 2 status/control register (USTCNT2) controls the overall operation of the UART 2 module.
The bit position assignments for this register are shown in the following register display. The settings for
this register are described in Table 14-10.
The bit position assignments for this register are shown in the following register display. The settings for
this register are described in Table 14-10.
USTCNT2
UART 2 Status/Control Register
0x(FF)FFF910
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
UEN
RX
EN
EN
TX
EN
CL
KM
PE
N
OD
D
ST
OP
8/7
OD
EN
CT
SD
SD
RX
FE
RX
HE
HE
RX
RE
RE
TX
EE
EE
TX
HE
TX
AE
AE
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 14-10. UART 2 Status/Control Register Description
Name
Description
Setting
UEN
Bit 15
Bit 15
UART 2 Enable—This bit enables the UART 2 module. This bit
resets to 0.
resets to 0.
Note:
When the UART 2 module is first enabled after a hard
reset and before the interrupts are enabled, set the UEN and
RXEN bits and perform a word read operation on the URX
register to initialize the FIFO and character status bits.
RXEN bits and perform a word read operation on the URX
register to initialize the FIFO and character status bits.
0 = UART 2 module is disabled
1 = UART 2 module is enabled
1 = UART 2 module is enabled
RXEN
Bit 14
Bit 14
Receiver Enable—This bit enables the receiver block. This bit
resets to 0.
resets to 0.
0 = Receiver is disabled and the
receive FIFO is flushed
1 = Receiver is enabled
TXEN
Bit 13
Bit 13
Transmitter Enable—This bit enables the transmitter block.
This bit resets to 0.
This bit resets to 0.
0 = Transmitter is disabled and the
transmit FIFO is flushed
1 = Transmitter is enabled
CLKM
Bit 12
Bit 12
Clock Mode Selection—This bit selects the receiver’s operat-
ing mode. When this bit is low, the receiver is in 16x mode, in
which it synchronizes to the incoming datastream and samples
at the perceived center of each bit period. When this bit is high,
the receiver is in 1x mode, in which it samples the datastream
on each rising edge of the bit clock. In 1x mode, the bit clock is
driven by CLK16. This bit resets to 0.
ing mode. When this bit is low, the receiver is in 16x mode, in
which it synchronizes to the incoming datastream and samples
at the perceived center of each bit period. When this bit is high,
the receiver is in 1x mode, in which it samples the datastream
on each rising edge of the bit clock. In 1x mode, the bit clock is
driven by CLK16. This bit resets to 0.
0 = 16x clock mode (asynchronous
mode)
1 = 1x clock mode (synchronous
mode)
PEN
Bit 11
Bit 11
Parity Enable—This bit controls the parity generator in the
transmitter and the parity checker in the receiver.
transmitter and the parity checker in the receiver.
0 = Parity is disabled
1 = Parity is enabled
1 = Parity is enabled
ODD
Bit 10
Bit 10
Odd Parity—This bit controls the sense of the parity generator
and checker. This bit has no function if the PEN bit is low.
and checker. This bit has no function if the PEN bit is low.
0 = Even parity
1 = Odd parity
1 = Odd parity
STOP
Bit 9
Bit 9
Stop Bit Transmission—This bit controls the number of stop
bits transmitted after a character. This bit has no effect on the
receiver, which expects one or more stop bits.
bits transmitted after a character. This bit has no effect on the
receiver, which expects one or more stop bits.
0 = One stop bit is transmitted
1 = Two stop bits are transmitted
1 = Two stop bits are transmitted
8/7
Bit 8
Bit 8
8- or 7-Bit—This bit controls the character length. When this
bit is set to 7-bit operation, the transmitter ignores data bit 7
and, when receiving, the receiver forces data bit 7 to 0.
bit is set to 7-bit operation, the transmitter ignores data bit 7
and, when receiving, the receiver forces data bit 7 to 0.
0 = 7-bit transmit-and-receive
character length
1 = 8-bit transmit-and-receive
character length