Motorola MC68VZ328 Manuale Utente
Programming Model
Universal Asynchronous Receiver/Transmitter 1 and 2
14-23
14.4.10
UART 2 Receiver Register
The UART 2 receiver (URX2) register indicates the status of the receiver FIFO and character data. The
FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data.
Before the receiver interrupts are enabled, the UEN and RXEN bits
FIFO status bits reflect the current status of the FIFO. At initial power up, these bits contain random data.
Before the receiver interrupts are enabled, the UEN and RXEN bits
in the USTCNT register should be set.
Reading the UART 2 receiver register initializes the FIFO status bits. The receiver interrupts can then be
enabled. However, the character status bits are only valid when read with the character bits in a 16-bit read
access. The bit position assignments for this register are shown in the following register display. The
settings for this register are described in Table 14-12.
enabled. However, the character status bits are only valid when read with the character bits in a 16-bit read
access. The bit position assignments for this register are shown in the following register display. The
settings for this register are described in Table 14-12.
URX2
UART 2 Receiver Register
0x(FF)FFF914
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
FIF
O
FU
LL
FIFO
HALF
DATA
READY
OLD
DATA
OVR
UN
FRAME
ERROR
BREAK
PARIT
Y
ERRO
R
RX DATA
TYPE
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 14-12. UART 2 Receiver Register Description
Name
Description
Setting
FIFO
FULL
Bit 15
FULL
Bit 15
FIFO Full (FIFO Status)—This read-only bit indicates that the
receiver FIFO is full and may generate an overrun. This bit gen-
erates a maskable interrupt.
receiver FIFO is full and may generate an overrun. This bit gen-
erates a maskable interrupt.
0 = Receiver FIFO is not full
1 = Receiver FIFO is full
1 = Receiver FIFO is full
FIFO
HALF
Bit 14
HALF
Bit 14
FIFO Half (FIFO Status)—This read-only bit indicates that the
receiver FIFO has four or fewer slots remaining in the FIFO.
This bit generates a maskable interrupt.
receiver FIFO has four or fewer slots remaining in the FIFO.
This bit generates a maskable interrupt.
0 = Receiver FIFO has more than
four slots remaining
1 = Receiver FIFO has four or fewer
slots remaining
DATA
READY
Bit 13
READY
Bit 13
Data Ready (FIFO Status)—This read-only bit indicates that at
least 1 byte is present in the receive FIFO. The character bits
are valid only while this bit is set. This bit generates a maskable
interrupt.
least 1 byte is present in the receive FIFO. The character bits
are valid only while this bit is set. This bit generates a maskable
interrupt.
0 = No data in the receiver FIFO
1 = Data in the receiver FIFO
1 = Data in the receiver FIFO
OLD
DATA
Bit 12
DATA
Bit 12
Old Data (FIFO Status)—This read-only bit indicates that data
in the FIFO is older than 30 bit times. It is useful in situations
where the FIFO FULL or FIFO HALF interrupts are used. If
there is data in the FIFO, but the amount is below the FIFO
HALF interrupt threshold, a maskable interrupt can be gener-
ated to alert the software that unread data is present. This bit
clears when the character bits are read.
in the FIFO is older than 30 bit times. It is useful in situations
where the FIFO FULL or FIFO HALF interrupts are used. If
there is data in the FIFO, but the amount is below the FIFO
HALF interrupt threshold, a maskable interrupt can be gener-
ated to alert the software that unread data is present. This bit
clears when the character bits are read.
0 = FIFO is empty or the data in the
FIFO is < 30 bit times old
1 = Data in the FIFO is > 30 bit times
old
OVRUN
Bit 11
Bit 11
FIFO Overrun (Character Status)—This read-only bit indi-
cates that the receiver overwrote data in the FIFO. The charac-
ter with this bit set is valid, but at least one previous character
was lost. In normal circumstances, this bit should never be set.
It indicates the software is not keeping up with the incoming
data rate. This bit is updated and valid for each received char-
acter.
cates that the receiver overwrote data in the FIFO. The charac-
ter with this bit set is valid, but at least one previous character
was lost. In normal circumstances, this bit should never be set.
It indicates the software is not keeping up with the incoming
data rate. This bit is updated and valid for each received char-
acter.
0 = No FIFO overrun occurred
1 = A FIFO overrun was detected
1 = A FIFO overrun was detected