Motorola MC68VZ328 Manuale Utente
ICE Operation
In-Circuit Emulation
16-3
16.1.2.1
Execution Breakpoints vs. Bus Breakpoints
An execution breakpoint is a breakpoint at which the current program execution stops and gives control to
the monitor. To set up a single execution breakpoint, initialize the compare and mask registers; set the SB,
PBEN, and CEN bits in the in-circuit emulation module control register (ICEMCR); and then clear the
BBIEN and HMDIS bits in the same register. For multiple execution breakpoint mode, clear the SB bit. A
bus breakpoint is a breakpoint at which the current program execution stops when there is a memory write
or read at a defined address location. To enter single bus breakpoint mode, set the SB, BBIEN, and CEN
bits, and then clear the PBEN and HMDIS bits. For multiple bus breakpoint mode, clear the SB bit.
the monitor. To set up a single execution breakpoint, initialize the compare and mask registers; set the SB,
PBEN, and CEN bits in the in-circuit emulation module control register (ICEMCR); and then clear the
BBIEN and HMDIS bits in the same register. For multiple execution breakpoint mode, clear the SB bit. A
bus breakpoint is a breakpoint at which the current program execution stops when there is a memory write
or read at a defined address location. To enter single bus breakpoint mode, set the SB, BBIEN, and CEN
bits, and then clear the PBEN and HMDIS bits. For multiple bus breakpoint mode, clear the SB bit.
16.1.3
Using the Signal Decoder
The emulator requires a local resident debug monitor to be mapped at a specific location that is transparent
to the user. This monitor resides in the dedicated memory space 0xFFFC0000–0xFFFCFFFF (64K), which
is selected by the EMUCS signal with internal DTACK generation. In emulation mode, the respected
memory map is reserved for the emulator, and memory should not be assigned to this area. The port size of
this monitor is 8-bit and the data bus is D[15:8].
to the user. This monitor resides in the dedicated memory space 0xFFFC0000–0xFFFCFFFF (64K), which
is selected by the EMUCS signal with internal DTACK generation. In emulation mode, the respected
memory map is reserved for the emulator, and memory should not be assigned to this area. The port size of
this monitor is 8-bit and the data bus is D[15:8].
The P/D signal indicates the characteristics of the current cycle. A 0 indicates a data access cycle
(FC[2:0] = x01), and a 1 indicates a program access (FC[2:0] = x10). The emulator uses this signal to
disassemble assembly code during trace.
(FC[2:0] = x01), and a 1 indicates a program access (FC[2:0] = x10). The emulator uses this signal to
disassemble assembly code during trace.
16.1.4
Using the Interrupt Gate Module
There are three level 7 interrupt sources: two are internal and one is external. An internal level 7 interrupt
is generated, if it is enabled, when a program or bus breakpoint is hit. An external level 7 interrupt is
directly connected to the EMUIRQ pin, which is a falling edge trigger signal. The level 7 interrupt vector
is hard coded to 0xFFFC0010 if the HMDIS bit in the ICEMCR register is clear. If HMDIS is set, refer to
Chapter 9, “Interrupt Controller,” for information about generating a level 7 interrupt vector number.
is generated, if it is enabled, when a program or bus breakpoint is hit. An external level 7 interrupt is
directly connected to the EMUIRQ pin, which is a falling edge trigger signal. The level 7 interrupt vector
is hard coded to 0xFFFC0010 if the HMDIS bit in the ICEMCR register is clear. If HMDIS is set, refer to
Chapter 9, “Interrupt Controller,” for information about generating a level 7 interrupt vector number.
When there is a level 7 interrupt, the software needs to check the in-circuit emulation module status
register (ICEMSR) to determine the source of the interrupt. Each of these interrupts can be cleared by
writing a 1 to the associated status bit. If the in-circuit emulation module is disabled, the EMUIRQ pin is
the only source for level 7 interrupts.
register (ICEMSR) to determine the source of the interrupt. Each of these interrupts can be cleared by
writing a 1 to the associated status bit. If the in-circuit emulation module is disabled, the EMUIRQ pin is
the only source for level 7 interrupts.
16.1.5
Using the A-Line Insertion Unit
The A-line insertion unit will physically replace the data bus contents with 0xA000 in an instruction fetch
cycle when the address of this bus cycle matches the breakpoint address. When an A-line insertion occurs,
the in-circuit emulation module will wait for an A-line exception to occur. If an A-line exception occurs, a
level 7 interrupt is generated to the signal that a program breakpoint hits.
cycle when the address of this bus cycle matches the breakpoint address. When an A-line insertion occurs,
the in-circuit emulation module will wait for an A-line exception to occur. If an A-line exception occurs, a
level 7 interrupt is generated to the signal that a program breakpoint hits.