Motorola MC68VZ328 Manuale Utente
4-12
MC68VZ328 User’s Manual
Introduction to the Power Control Module
4.5.1.4
Sleep Mode
Unlike burst or doze mode, sleep mode disables all of the clocks in the MC68VZ328 with the exception of
the CLK32. The output of the PLL in the CGM is disabled in sleep mode through setting the DISPLL bit in
the PLLCR register. Only the 32 kHz clock works to keep the real-time clock operational. Wake-up events
activate the PLL, and the system clock starts operating after a delay determined by the WKSEL setting in
the PLLCR.
the CLK32. The output of the PLL in the CGM is disabled in sleep mode through setting the DISPLL bit in
the PLLCR register. Only the 32 kHz clock works to keep the real-time clock operational. Wake-up events
activate the PLL, and the system clock starts operating after a delay determined by the WKSEL setting in
the PLLCR.
Other events that occur during sleep mode include:
•
All Address Bus signals are in the active state of the last bus cycle.
•
All data bus pins (D15–D0) are individually pulled up with 1-megaohm resistors.
•
If CLK32 is selected as the clock source, the general-purpose timer operates even while the PLL is
in sleep mode.
in sleep mode.
•
The RTC interrupt status register can post interrupts while the system clock is in doze or sleep mode.
4.5.2
CGM Operation During Sleep Mode
Shutting down the PLL to place the system in sleep mode is similar to the process used to change the
frequency. The difference is that the system can be awakened only by a wake-up event or reset. Before
shutting the PLL down, make sure that all peripheral devices are prepared for shutdown. The PLL shuts
down 30 clock cycles of SYSCLK after the DISPLL bit is set in the PLLCR, allowing sufficient time to
execute the stop instruction. When a wake-up event occurs, the PLL is enabled, and after a delay
determined by the WKSEL setting in the PLLCR, the PLLCLK begins, as do as the rest of the clocks in the
divider chain of the CGM. The CPU executes an interrupt service routine for the level of the wake-up
event.
frequency. The difference is that the system can be awakened only by a wake-up event or reset. Before
shutting the PLL down, make sure that all peripheral devices are prepared for shutdown. The PLL shuts
down 30 clock cycles of SYSCLK after the DISPLL bit is set in the PLLCR, allowing sufficient time to
execute the stop instruction. When a wake-up event occurs, the PLL is enabled, and after a delay
determined by the WKSEL setting in the PLLCR, the PLLCLK begins, as do as the rest of the clocks in the
divider chain of the CGM. The CPU executes an interrupt service routine for the level of the wake-up
event.
After the rte instruction in the wake-up service routine, the CPU returns and starts execution on the
instruction following the stop instruction. Example 4-2 illustrates a typical shutdown sequence. It assumes
that all peripherals have been shut down before the PLL is stopped.
instruction following the stop instruction. Example 4-2 illustrates a typical shutdown sequence. It assumes
that all peripherals have been shut down before the PLL is stopped.
Example 4-2. Shutdown Example
IRQMASK equ wake-up_mask_level
ori.b #$8,PLLCONTROL+1
;disable the PLL (in 30 clocks)
stop #IRQMASK
;stop, enable wake-up events
;the PLL shuts down here
;The PLL has reacquired lock and SYSCLK is stable
;interrupt service occurs here
;The PLL has reacquired lock and SYSCLK is stable
;interrupt service occurs here
rts
;the system is operating
4.5.3
Burst Mode Operation
Figure 4-4 on page 4-13 shows a simplified block diagram of the PCM. When operating at 100 percent, the
SYSCLK input is unaffected by burst-width control appearing as CPUCLK from the clock control. When a
value has been placed in the width field of the PCTLR, the burst-width control allows the SYSCLK signal
through to the clock control until the CPU clock’s time slot has expired and is to be disabled. At that time
the clock control requests the bus from the CPU. After the bus is granted, the CPUCLK stops. A bus grant
to the DMA controller is asserted, allowing the DMA controller complete access to the bus.
SYSCLK input is unaffected by burst-width control appearing as CPUCLK from the clock control. When a
value has been placed in the width field of the PCTLR, the burst-width control allows the SYSCLK signal
through to the clock control until the CPU clock’s time slot has expired and is to be disabled. At that time
the clock control requests the bus from the CPU. After the bus is granted, the CPUCLK stops. A bus grant
to the DMA controller is asserted, allowing the DMA controller complete access to the bus.