Motorola MC68VZ328 Manuale Utente
System Control
5-1
Chapter 5
System Control
This chapter describes the system control register of the MC68VZ328 microprocessor. The system control
register enables system software to control and customize the following functions:
register enables system software to control and customize the following functions:
•
Access permission from the internal peripheral registers
•
Address space of the internal peripheral registers
•
Bus time-out control and status (bus error generator)
5.1
System Control Operation
The on-chip resources use a reserved 4,096-byte block of address space for their registers. This block is
mapped beginning at location 0xFFFFF000 (32-bit) or 0xXXFFF000 (24-bit, where XX is “don’t care”) on
reset. The DMAP bit in the system control register disables double mapping in a 32-bit system. If this bit is
cleared, the on-chip peripheral registers appear only at the top of the 4 Gbyte address range starting at
0xFFFFF000.
mapped beginning at location 0xFFFFF000 (32-bit) or 0xXXFFF000 (24-bit, where XX is “don’t care”) on
reset. The DMAP bit in the system control register disables double mapping in a 32-bit system. If this bit is
cleared, the on-chip peripheral registers appear only at the top of the 4 Gbyte address range starting at
0xFFFFF000.
The system control register provides control of system operation functions such as bus interface and
watchdog protection. The system control register contains status bits that allow exception handler code to
interrogate the cause of both exceptions and resets. The bus time-out monitor and the watchdog timer
provide system protection. The bus time-out monitor generates a bus error when a bus cycle is not
terminated by the DTACK signal after 128 clock cycles have elapsed.
watchdog protection. The system control register contains status bits that allow exception handler code to
interrogate the cause of both exceptions and resets. The bus time-out monitor and the watchdog timer
provide system protection. The bus time-out monitor generates a bus error when a bus cycle is not
terminated by the DTACK signal after 128 clock cycles have elapsed.
5.1.1
Bus Monitors and Watchdog Timers
The bus error time-out logic consists of a bus time-out monitor that, when enabled, begins to count clock
cycles as the internal AS pin is asserted for internal or external bus accesses. The deassertion of AS
normally terminates the count, but if the count reaches terminal count before AS is deasserted, BERR is
asserted until AS is deasserted. The bus error time-out logic consists of 1 control bit and 1 status bit in the
system control register. The BETO bit in the system control register is set after a bus time out, which may
indicate a write-protect violation or privilege.
cycles as the internal AS pin is asserted for internal or external bus accesses. The deassertion of AS
normally terminates the count, but if the count reaches terminal count before AS is deasserted, BERR is
asserted until AS is deasserted. The bus error time-out logic consists of 1 control bit and 1 status bit in the
system control register. The BETO bit in the system control register is set after a bus time out, which may
indicate a write-protect violation or privilege.
The watchdog timer resets the MC68VZ328 if it is enabled and not cleared or disabled before reaching
terminal count. The watchdog timer is enabled at reset.
terminal count. The watchdog timer is enabled at reset.