IBM 150 Manuale Utente
Hardware Overview
29
2.2.2 Hardware Design for the RS/6000 43P 7043 Model 260
Figure 9 on page 30 shows the system block diagram for the Model 260. This
workstation is a 1- or 2-way symmetric multiprocessing system using the
64-bit 200 MHz POWER3 processor. The processor subsystem is
implemented on pluggable processor cards. If two cards are installed in the
system, they must both be the same type or the system will not power on.
workstation is a 1- or 2-way symmetric multiprocessing system using the
64-bit 200 MHz POWER3 processor. The processor subsystem is
implemented on pluggable processor cards. If two cards are installed in the
system, they must both be the same type or the system will not power on.
The POWER3 processor card has two main components:
• POWER3 chip itself
• 4MB L2 cache
The controller for the L2 cache is integrated on the POWER3 chip, so there is
no need for the separate X5 cache that exists on some RS/6000 systems,
such as the Model F50.
no need for the separate X5 cache that exists on some RS/6000 systems,
such as the Model F50.
Three main buses are used in this system design, namely:
• System bus
• Memory bus
• I/O bus
The system bus within the RS/6000 Model 260 is an SMP 6XX high
performance bus. The POWER3 processor delivers the SMP server bus
directly, and therefore can have direct connectivity to the memory controller
chip. Each POWER3 CPU has two paths leading from the processor, namely
an address bus (64-bit) and a data bus (128-bit), highlighting the true split
transaction capability of the 6XX bus. The address bus of one CPU merges
with the address bus of the other to create a single input to the Address
Controller unit. Similarly, the data bus of one CPU merges with the data bus
of the other, creating a single input to the Data Controller unit.
performance bus. The POWER3 processor delivers the SMP server bus
directly, and therefore can have direct connectivity to the memory controller
chip. Each POWER3 CPU has two paths leading from the processor, namely
an address bus (64-bit) and a data bus (128-bit), highlighting the true split
transaction capability of the 6XX bus. The address bus of one CPU merges
with the address bus of the other to create a single input to the Address
Controller unit. Similarly, the data bus of one CPU merges with the data bus
of the other, creating a single input to the Data Controller unit.
The Address Controller unit and the Data Controller unit, both semi-custom
CMOS5S chips, are separate partitions of a recently developed enhanced
memory controller unit. This chipset supports running the bus at 100 MHz. A
clock distribution chip was designed and placed on each memory card to
achieve 100 MHz performance.
CMOS5S chips, are separate partitions of a recently developed enhanced
memory controller unit. This chipset supports running the bus at 100 MHz. A
clock distribution chip was designed and placed on each memory card to
achieve 100 MHz performance.